TimeQuest Timing Analyzer report for DE0_NANO_G_Sensor
Thu Aug 31 22:58:01 2017
Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. Clocks
  5. Slow 1200mV 85C Model Fmax Summary
  6. Timing Closure Recommendations
  7. Slow 1200mV 85C Model Setup Summary
  8. Slow 1200mV 85C Model Hold Summary
  9. Slow 1200mV 85C Model Recovery Summary
 10. Slow 1200mV 85C Model Removal Summary
 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
 12. Slow 1200mV 85C Model Setup: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'
 13. Slow 1200mV 85C Model Setup: 'CLOCK_50'
 14. Slow 1200mV 85C Model Hold: 'CLOCK_50'
 15. Slow 1200mV 85C Model Hold: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'
 16. Slow 1200mV 85C Model Recovery: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'
 17. Slow 1200mV 85C Model Recovery: 'CLOCK_50'
 18. Slow 1200mV 85C Model Removal: 'CLOCK_50'
 19. Slow 1200mV 85C Model Removal: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'
 20. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'
 21. Slow 1200mV 85C Model Minimum Pulse Width: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'
 22. Setup Times
 23. Hold Times
 24. Clock to Output Times
 25. Minimum Clock to Output Times
 26. Propagation Delay
 27. Minimum Propagation Delay
 28. Output Enable Times
 29. Minimum Output Enable Times
 30. Output Disable Times
 31. Minimum Output Disable Times
 32. Slow 1200mV 85C Model Metastability Report
 33. Slow 1200mV 0C Model Fmax Summary
 34. Slow 1200mV 0C Model Setup Summary
 35. Slow 1200mV 0C Model Hold Summary
 36. Slow 1200mV 0C Model Recovery Summary
 37. Slow 1200mV 0C Model Removal Summary
 38. Slow 1200mV 0C Model Minimum Pulse Width Summary
 39. Slow 1200mV 0C Model Setup: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'
 40. Slow 1200mV 0C Model Setup: 'CLOCK_50'
 41. Slow 1200mV 0C Model Hold: 'CLOCK_50'
 42. Slow 1200mV 0C Model Hold: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'
 43. Slow 1200mV 0C Model Recovery: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'
 44. Slow 1200mV 0C Model Recovery: 'CLOCK_50'
 45. Slow 1200mV 0C Model Removal: 'CLOCK_50'
 46. Slow 1200mV 0C Model Removal: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'
 47. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
 48. Slow 1200mV 0C Model Minimum Pulse Width: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'
 49. Setup Times
 50. Hold Times
 51. Clock to Output Times
 52. Minimum Clock to Output Times
 53. Propagation Delay
 54. Minimum Propagation Delay
 55. Output Enable Times
 56. Minimum Output Enable Times
 57. Output Disable Times
 58. Minimum Output Disable Times
 59. Slow 1200mV 0C Model Metastability Report
 60. Fast 1200mV 0C Model Setup Summary
 61. Fast 1200mV 0C Model Hold Summary
 62. Fast 1200mV 0C Model Recovery Summary
 63. Fast 1200mV 0C Model Removal Summary
 64. Fast 1200mV 0C Model Minimum Pulse Width Summary
 65. Fast 1200mV 0C Model Setup: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'
 66. Fast 1200mV 0C Model Setup: 'CLOCK_50'
 67. Fast 1200mV 0C Model Hold: 'CLOCK_50'
 68. Fast 1200mV 0C Model Hold: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'
 69. Fast 1200mV 0C Model Recovery: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'
 70. Fast 1200mV 0C Model Recovery: 'CLOCK_50'
 71. Fast 1200mV 0C Model Removal: 'CLOCK_50'
 72. Fast 1200mV 0C Model Removal: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'
 73. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
 74. Fast 1200mV 0C Model Minimum Pulse Width: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'
 75. Setup Times
 76. Hold Times
 77. Clock to Output Times
 78. Minimum Clock to Output Times
 79. Propagation Delay
 80. Minimum Propagation Delay
 81. Output Enable Times
 82. Minimum Output Enable Times
 83. Output Disable Times
 84. Minimum Output Disable Times
 85. Fast 1200mV 0C Model Metastability Report
 86. Multicorner Timing Analysis Summary
 87. Setup Times
 88. Hold Times
 89. Clock to Output Times
 90. Minimum Clock to Output Times
 91. Progagation Delay
 92. Minimum Progagation Delay
 93. Board Trace Model Assignments
 94. Input Transition Times
 95. Signal Integrity Metrics (Slow 1200mv 0c Model)
 96. Signal Integrity Metrics (Slow 1200mv 85c Model)
 97. Signal Integrity Metrics (Fast 1200mv 0c Model)
 98. Setup Transfers
 99. Hold Transfers
100. Recovery Transfers
101. Removal Transfers
102. Report TCCS
103. Report RSKM
104. Unconstrained Paths
105. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                       ;
+--------------------+----------------------------------------------------+
; Quartus II Version ; Version 13.0.0 Build 156 04/24/2013 SJ Web Edition ;
; Revision Name      ; DE0_NANO_G_Sensor                                  ;
; Device Family      ; Cyclone IV E                                       ;
; Device Name        ; EP4CE22F17C6                                       ;
; Timing Models      ; Final                                              ;
; Delay Model        ; Combined                                           ;
; Rise/Fall Delays   ; Enabled                                            ;
+--------------------+----------------------------------------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 8      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                ;
+------------------------------------------------------+-----------+---------+-----------+---------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+--------------------------------------------------------+----------------------------------------------------------+
; Clock Name                                           ; Type      ; Period  ; Frequency ; Rise    ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master   ; Source                                                 ; Targets                                                  ;
+------------------------------------------------------+-----------+---------+-----------+---------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+--------------------------------------------------------+----------------------------------------------------------+
; CLOCK_50                                             ; Base      ; 20.000  ; 50.0 MHz  ; 0.000   ; 10.000  ;            ;           ;             ;       ;        ;           ;            ;          ;          ;                                                        ; { CLOCK_50 }                                             ;
; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 500.000 ; 2.0 MHz   ; 200.000 ; 450.000 ; 50.00      ; 25        ; 1           ; 144.0 ;        ;           ;            ; false    ; CLOCK_50 ; u_spipll|altpll_component|auto_generated|pll1|inclk[0] ; { u_spipll|altpll_component|auto_generated|pll1|clk[0] } ;
; u_spipll|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 500.000 ; 2.0 MHz   ; 166.666 ; 416.666 ; 50.00      ; 25        ; 1           ; 120.0 ;        ;           ;            ; false    ; CLOCK_50 ; u_spipll|altpll_component|auto_generated|pll1|inclk[0] ; { u_spipll|altpll_component|auto_generated|pll1|clk[1] } ;
+------------------------------------------------------+-----------+---------+-----------+---------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+--------------------------------------------------------+----------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                                                  ;
+------------+-----------------+------------------------------------------------------+---------------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                           ; Note                                                          ;
+------------+-----------------+------------------------------------------------------+---------------------------------------------------------------+
; 260.42 MHz ; 250.0 MHz       ; CLOCK_50                                             ; limit due to minimum period restriction (max I/O toggle rate) ;
; 271.3 MHz  ; 271.3 MHz       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;                                                               ;
+------------+-----------------+------------------------------------------------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+-------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                           ;
+------------------------------------------------------+--------+---------------+
; Clock                                                ; Slack  ; End Point TNS ;
+------------------------------------------------------+--------+---------------+
; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 15.095 ; 0.000         ;
; CLOCK_50                                             ; 16.160 ; 0.000         ;
+------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                           ;
+------------------------------------------------------+-------+---------------+
; Clock                                                ; Slack ; End Point TNS ;
+------------------------------------------------------+-------+---------------+
; CLOCK_50                                             ; 0.358 ; 0.000         ;
; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.358 ; 0.000         ;
+------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                        ;
+------------------------------------------------------+--------+---------------+
; Clock                                                ; Slack  ; End Point TNS ;
+------------------------------------------------------+--------+---------------+
; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 15.083 ; 0.000         ;
; CLOCK_50                                             ; 17.330 ; 0.000         ;
+------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                        ;
+------------------------------------------------------+-------+---------------+
; Clock                                                ; Slack ; End Point TNS ;
+------------------------------------------------------+-------+---------------+
; CLOCK_50                                             ; 1.509 ; 0.000         ;
; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 3.110 ; 0.000         ;
+------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                              ;
+------------------------------------------------------+---------+---------------+
; Clock                                                ; Slack   ; End Point TNS ;
+------------------------------------------------------+---------+---------------+
; CLOCK_50                                             ; 9.595   ; 0.000         ;
; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 249.748 ; 0.000         ;
+------------------------------------------------------+---------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                      ;
+---------+--------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                  ; To Node                                                                    ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+---------+--------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 15.095  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 2.503      ;
; 15.095  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 2.503      ;
; 15.095  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 2.503      ;
; 15.095  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 2.503      ;
; 15.095  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 2.503      ;
; 15.125  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.338     ; 2.482      ;
; 15.125  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.338     ; 2.482      ;
; 15.125  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.338     ; 2.482      ;
; 15.125  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.338     ; 2.482      ;
; 15.125  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|oDATA_L[5]                                   ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.338     ; 2.482      ;
; 15.292  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|low_byte_data[6]                             ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 2.306      ;
; 15.292  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|low_byte_data[7]                             ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 2.306      ;
; 15.292  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|low_byte_data[5]                             ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 2.306      ;
; 15.318  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[8]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 2.280      ;
; 15.318  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[9]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 2.280      ;
; 15.604  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.994      ;
; 15.604  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.994      ;
; 15.604  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.994      ;
; 15.604  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[1]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.994      ;
; 15.604  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[3]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.994      ;
; 15.604  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[2]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.994      ;
; 15.604  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[6]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.994      ;
; 15.762  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[0] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.836      ;
; 15.762  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[1] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.836      ;
; 15.762  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[2] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.836      ;
; 15.762  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[3] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.836      ;
; 15.762  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[4] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.836      ;
; 15.762  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[5] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.836      ;
; 15.762  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[6] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.836      ;
; 15.762  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[7] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.836      ;
; 16.269  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|read_ready                                   ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.329      ;
; 496.314 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.622      ;
; 496.314 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.622      ;
; 496.314 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.622      ;
; 496.314 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.622      ;
; 496.314 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.622      ;
; 496.323 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.613      ;
; 496.323 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.613      ;
; 496.323 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.613      ;
; 496.323 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.613      ;
; 496.323 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.613      ;
; 496.332 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.604      ;
; 496.332 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.604      ;
; 496.332 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.604      ;
; 496.332 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[1]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.604      ;
; 496.332 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[3]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.604      ;
; 496.332 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[2]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.604      ;
; 496.332 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[6]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.604      ;
; 496.341 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.595      ;
; 496.341 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.595      ;
; 496.341 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.595      ;
; 496.341 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[1]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.595      ;
; 496.341 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[3]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.595      ;
; 496.341 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[2]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.595      ;
; 496.341 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[6]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.595      ;
; 496.378 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.065     ; 3.552      ;
; 496.378 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.065     ; 3.552      ;
; 496.378 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.065     ; 3.552      ;
; 496.378 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.065     ; 3.552      ;
; 496.378 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|oDATA_L[5]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.065     ; 3.552      ;
; 496.387 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.065     ; 3.543      ;
; 496.387 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.065     ; 3.543      ;
; 496.387 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.065     ; 3.543      ;
; 496.387 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.065     ; 3.543      ;
; 496.387 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|oDATA_L[5]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.065     ; 3.543      ;
; 496.415 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.521      ;
; 496.415 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.521      ;
; 496.415 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.521      ;
; 496.415 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.521      ;
; 496.415 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.521      ;
; 496.433 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.503      ;
; 496.433 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.503      ;
; 496.433 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.503      ;
; 496.433 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[1]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.503      ;
; 496.433 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[3]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.503      ;
; 496.433 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[2]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.503      ;
; 496.433 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[6]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.503      ;
; 496.479 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.065     ; 3.451      ;
; 496.479 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.065     ; 3.451      ;
; 496.479 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.065     ; 3.451      ;
; 496.479 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.065     ; 3.451      ;
; 496.479 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|oDATA_L[5]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.065     ; 3.451      ;
; 496.552 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|low_byte_data[6]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.384      ;
; 496.552 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|low_byte_data[7]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.384      ;
; 496.552 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|low_byte_data[5]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.384      ;
; 496.556 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[8]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.380      ;
; 496.556 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[9]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.380      ;
; 496.561 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|low_byte_data[6]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.375      ;
; 496.561 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|low_byte_data[7]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.375      ;
; 496.561 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|low_byte_data[5]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.375      ;
; 496.565 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[8]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.371      ;
; 496.565 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[9]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.371      ;
; 496.576 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.360      ;
; 496.576 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.360      ;
; 496.576 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.360      ;
; 496.576 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.360      ;
; 496.576 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.360      ;
; 496.594 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.342      ;
; 496.594 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.342      ;
; 496.594 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.059     ; 3.342      ;
+---------+--------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'CLOCK_50'                                                                                                                        ;
+--------+----------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                              ; To Node                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; 16.160 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.774      ;
; 16.201 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.733      ;
; 16.211 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.724      ;
; 16.255 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.679      ;
; 16.264 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.670      ;
; 16.313 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.621      ;
; 16.413 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.521      ;
; 16.500 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.434      ;
; 16.502 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.432      ;
; 16.522 ; led_driver:u_led_driver|int2_count[4]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.413      ;
; 16.523 ; led_driver:u_led_driver|int2_count[9]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.411      ;
; 16.553 ; led_driver:u_led_driver|int2_count[7]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.382      ;
; 16.560 ; led_driver:u_led_driver|int2_count[12] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.374      ;
; 16.563 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.371      ;
; 16.573 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.362      ;
; 16.589 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.345      ;
; 16.598 ; led_driver:u_led_driver|int2_count[8]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.336      ;
; 16.618 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.316      ;
; 16.626 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.308      ;
; 16.636 ; led_driver:u_led_driver|int2_count[6]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.299      ;
; 16.646 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.288      ;
; 16.656 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.279      ;
; 16.659 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.275      ;
; 16.666 ; led_driver:u_led_driver|int2_count[11] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.268      ;
; 16.669 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.266      ;
; 16.675 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.259      ;
; 16.709 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.225      ;
; 16.713 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.221      ;
; 16.717 ; led_driver:u_led_driver|int2_count[10] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.217      ;
; 16.722 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.212      ;
; 16.729 ; led_driver:u_led_driver|int2_count[17] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.205      ;
; 16.733 ; led_driver:u_led_driver|int2_count[14] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.201      ;
; 16.758 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.176      ;
; 16.759 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.175      ;
; 16.771 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.163      ;
; 16.785 ; led_driver:u_led_driver|int2_count[4]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.150      ;
; 16.798 ; led_driver:u_led_driver|int2_count[12] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.136      ;
; 16.800 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.134      ;
; 16.810 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.125      ;
; 16.842 ; led_driver:u_led_driver|int2_count[16] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.092      ;
; 16.843 ; led_driver:u_led_driver|int2_count[8]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.091      ;
; 16.851 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.084      ;
; 16.854 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.080      ;
; 16.863 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.071      ;
; 16.864 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.070      ;
; 16.868 ; led_driver:u_led_driver|int2_count[15] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 3.064      ;
; 16.872 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.062      ;
; 16.874 ; led_driver:u_led_driver|int2_count[4]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.061      ;
; 16.885 ; led_driver:u_led_driver|int2_count[9]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.049      ;
; 16.887 ; led_driver:u_led_driver|int2_count[12] ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.047      ;
; 16.900 ; led_driver:u_led_driver|int2_count[6]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.035      ;
; 16.905 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.029      ;
; 16.912 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.022      ;
; 16.913 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.021      ;
; 16.915 ; led_driver:u_led_driver|int2_count[7]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.020      ;
; 16.915 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.020      ;
; 16.923 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[19] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.011      ;
; 16.923 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.011      ;
; 16.923 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.012      ;
; 16.932 ; led_driver:u_led_driver|int2_count[8]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.002      ;
; 16.938 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 2.997      ;
; 16.947 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[21] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.987      ;
; 16.959 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.975      ;
; 16.962 ; led_driver:u_led_driver|int2_count[10] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.972      ;
; 16.964 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.970      ;
; 16.967 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.967      ;
; 16.968 ; led_driver:u_led_driver|int2_count[9]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.966      ;
; 16.974 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 2.961      ;
; 16.975 ; led_driver:u_led_driver|int2_count[14] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.959      ;
; 16.976 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.958      ;
; 16.980 ; led_driver:u_led_driver|int2_count[4]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 2.955      ;
; 16.981 ; led_driver:u_led_driver|int2_count[9]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.953      ;
; 16.988 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 2.947      ;
; 16.989 ; led_driver:u_led_driver|int2_count[6]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 2.946      ;
; 16.998 ; led_driver:u_led_driver|int2_count[7]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 2.937      ;
; 16.998 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 2.938      ;
; 17.010 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[19] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.924      ;
; 17.011 ; led_driver:u_led_driver|int2_count[7]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 2.924      ;
; 17.017 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.917      ;
; 17.017 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.917      ;
; 17.018 ; led_driver:u_led_driver|int2_count[12] ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.916      ;
; 17.018 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.916      ;
; 17.025 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.909      ;
; 17.027 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.907      ;
; 17.028 ; led_driver:u_led_driver|int2_count[11] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.906      ;
; 17.034 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[21] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.900      ;
; 17.041 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.893      ;
; 17.051 ; led_driver:u_led_driver|int2_count[10] ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.883      ;
; 17.051 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 2.884      ;
; 17.056 ; led_driver:u_led_driver|int2_count[8]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.878      ;
; 17.059 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.875      ;
; 17.060 ; led_driver:u_led_driver|int2_count[20] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.874      ;
; 17.060 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[19] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.874      ;
; 17.063 ; reset_delay:u_reset_delay|cont[1]      ; reset_delay:u_reset_delay|cont[20]     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 2.872      ;
; 17.064 ; led_driver:u_led_driver|int2_count[14] ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.870      ;
; 17.070 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[19] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 2.865      ;
; 17.076 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.858      ;
; 17.082 ; led_driver:u_led_driver|int2_count[16] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.852      ;
; 17.082 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.852      ;
; 17.084 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[21] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 2.850      ;
+--------+----------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'CLOCK_50'                                                                                                                        ;
+-------+----------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                              ; To Node                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.358 ; reset_delay:u_reset_delay|cont[20]     ; reset_delay:u_reset_delay|cont[20]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; led_driver:u_led_driver|int2_count[23] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.361 ; reset_delay:u_reset_delay|cont[0]      ; reset_delay:u_reset_delay|cont[0]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.580      ;
; 0.548 ; reset_delay:u_reset_delay|cont[8]      ; reset_delay:u_reset_delay|cont[8]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.767      ;
; 0.548 ; reset_delay:u_reset_delay|cont[10]     ; reset_delay:u_reset_delay|cont[10]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.767      ;
; 0.549 ; reset_delay:u_reset_delay|cont[6]      ; reset_delay:u_reset_delay|cont[6]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.768      ;
; 0.549 ; reset_delay:u_reset_delay|cont[14]     ; reset_delay:u_reset_delay|cont[14]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.768      ;
; 0.550 ; reset_delay:u_reset_delay|cont[12]     ; reset_delay:u_reset_delay|cont[12]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.769      ;
; 0.550 ; reset_delay:u_reset_delay|cont[16]     ; reset_delay:u_reset_delay|cont[16]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.769      ;
; 0.551 ; reset_delay:u_reset_delay|cont[11]     ; reset_delay:u_reset_delay|cont[11]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.770      ;
; 0.551 ; reset_delay:u_reset_delay|cont[17]     ; reset_delay:u_reset_delay|cont[17]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.770      ;
; 0.552 ; reset_delay:u_reset_delay|cont[2]      ; reset_delay:u_reset_delay|cont[2]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.771      ;
; 0.552 ; reset_delay:u_reset_delay|cont[4]      ; reset_delay:u_reset_delay|cont[4]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.771      ;
; 0.552 ; reset_delay:u_reset_delay|cont[9]      ; reset_delay:u_reset_delay|cont[9]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.771      ;
; 0.553 ; reset_delay:u_reset_delay|cont[7]      ; reset_delay:u_reset_delay|cont[7]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.772      ;
; 0.553 ; reset_delay:u_reset_delay|cont[13]     ; reset_delay:u_reset_delay|cont[13]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.772      ;
; 0.553 ; reset_delay:u_reset_delay|cont[18]     ; reset_delay:u_reset_delay|cont[18]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.772      ;
; 0.554 ; reset_delay:u_reset_delay|cont[3]      ; reset_delay:u_reset_delay|cont[3]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.773      ;
; 0.554 ; reset_delay:u_reset_delay|cont[5]      ; reset_delay:u_reset_delay|cont[5]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.773      ;
; 0.554 ; reset_delay:u_reset_delay|cont[15]     ; reset_delay:u_reset_delay|cont[15]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.773      ;
; 0.555 ; reset_delay:u_reset_delay|cont[19]     ; reset_delay:u_reset_delay|cont[19]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.774      ;
; 0.564 ; reset_delay:u_reset_delay|cont[0]      ; reset_delay:u_reset_delay|cont[1]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.783      ;
; 0.591 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.810      ;
; 0.673 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[11] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 0.890      ;
; 0.688 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 0.905      ;
; 0.690 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[3]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 0.907      ;
; 0.696 ; reset_delay:u_reset_delay|cont[1]      ; reset_delay:u_reset_delay|cont[1]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.915      ;
; 0.697 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[0]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 0.914      ;
; 0.698 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[2]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 0.915      ;
; 0.704 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[21] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.922      ;
; 0.704 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.922      ;
; 0.735 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[10] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.953      ;
; 0.736 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.954      ;
; 0.737 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[8]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.955      ;
; 0.738 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[9]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.956      ;
; 0.742 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[5]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.960      ;
; 0.742 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.960      ;
; 0.743 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[11] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.961      ;
; 0.745 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.963      ;
; 0.747 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.965      ;
; 0.748 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[13] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.966      ;
; 0.749 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.967      ;
; 0.750 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.968      ;
; 0.776 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.996      ;
; 0.780 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_d[1]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 1.000      ;
; 0.783 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[7]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.000      ;
; 0.788 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[19] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.006      ;
; 0.811 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.029      ;
; 0.821 ; reset_delay:u_reset_delay|cont[10]     ; reset_delay:u_reset_delay|cont[11]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 1.042      ;
; 0.823 ; reset_delay:u_reset_delay|cont[8]      ; reset_delay:u_reset_delay|cont[9]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.042      ;
; 0.824 ; reset_delay:u_reset_delay|cont[6]      ; reset_delay:u_reset_delay|cont[7]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.043      ;
; 0.824 ; reset_delay:u_reset_delay|cont[12]     ; reset_delay:u_reset_delay|cont[13]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.043      ;
; 0.824 ; reset_delay:u_reset_delay|cont[14]     ; reset_delay:u_reset_delay|cont[15]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.043      ;
; 0.825 ; reset_delay:u_reset_delay|cont[16]     ; reset_delay:u_reset_delay|cont[17]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.044      ;
; 0.826 ; reset_delay:u_reset_delay|cont[2]      ; reset_delay:u_reset_delay|cont[3]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.045      ;
; 0.826 ; reset_delay:u_reset_delay|cont[4]      ; reset_delay:u_reset_delay|cont[5]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.045      ;
; 0.827 ; reset_delay:u_reset_delay|cont[18]     ; reset_delay:u_reset_delay|cont[19]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.046      ;
; 0.838 ; reset_delay:u_reset_delay|cont[11]     ; reset_delay:u_reset_delay|cont[12]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.057      ;
; 0.838 ; reset_delay:u_reset_delay|cont[0]      ; reset_delay:u_reset_delay|cont[2]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.057      ;
; 0.839 ; reset_delay:u_reset_delay|cont[9]      ; reset_delay:u_reset_delay|cont[10]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.058      ;
; 0.839 ; reset_delay:u_reset_delay|cont[17]     ; reset_delay:u_reset_delay|cont[18]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.058      ;
; 0.839 ; reset_delay:u_reset_delay|cont[9]      ; reset_delay:u_reset_delay|cont[11]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 1.060      ;
; 0.840 ; reset_delay:u_reset_delay|cont[7]      ; reset_delay:u_reset_delay|cont[8]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.059      ;
; 0.840 ; reset_delay:u_reset_delay|cont[13]     ; reset_delay:u_reset_delay|cont[14]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.059      ;
; 0.840 ; reset_delay:u_reset_delay|cont[11]     ; reset_delay:u_reset_delay|cont[13]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.059      ;
; 0.840 ; reset_delay:u_reset_delay|cont[0]      ; reset_delay:u_reset_delay|cont[3]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.059      ;
; 0.841 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[1]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.060      ;
; 0.841 ; reset_delay:u_reset_delay|cont[5]      ; reset_delay:u_reset_delay|cont[6]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.060      ;
; 0.841 ; reset_delay:u_reset_delay|cont[15]     ; reset_delay:u_reset_delay|cont[16]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.060      ;
; 0.841 ; reset_delay:u_reset_delay|cont[3]      ; reset_delay:u_reset_delay|cont[4]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.060      ;
; 0.841 ; led_driver:u_led_driver|int2_count[22] ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.060      ;
; 0.841 ; reset_delay:u_reset_delay|cont[17]     ; reset_delay:u_reset_delay|cont[19]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.060      ;
; 0.842 ; reset_delay:u_reset_delay|cont[7]      ; reset_delay:u_reset_delay|cont[9]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.061      ;
; 0.842 ; reset_delay:u_reset_delay|cont[13]     ; reset_delay:u_reset_delay|cont[15]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.061      ;
; 0.843 ; led_driver:u_led_driver|int2_count[21] ; led_driver:u_led_driver|int2_count[21] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.062      ;
; 0.843 ; reset_delay:u_reset_delay|cont[5]      ; reset_delay:u_reset_delay|cont[7]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.062      ;
; 0.843 ; reset_delay:u_reset_delay|cont[15]     ; reset_delay:u_reset_delay|cont[17]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.062      ;
; 0.843 ; reset_delay:u_reset_delay|cont[3]      ; reset_delay:u_reset_delay|cont[5]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.062      ;
; 0.845 ; led_driver:u_led_driver|int2_count[4]  ; led_driver:u_led_driver|int2_count[4]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.064      ;
; 0.847 ; led_driver:u_led_driver|int2_count[6]  ; led_driver:u_led_driver|int2_count[6]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.066      ;
; 0.863 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.080      ;
; 0.864 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[13] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.081      ;
; 0.865 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.082      ;
; 0.865 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.082      ;
; 0.875 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.092      ;
; 0.881 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[0]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.099      ;
; 0.882 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[2]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.100      ;
; 0.884 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.101      ;
; 0.884 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[5]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.101      ;
; 0.885 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[8]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.102      ;
; 0.886 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[9]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.103      ;
; 0.888 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[10] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.105      ;
; 0.894 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[3]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.112      ;
; 0.916 ; reset_delay:u_reset_delay|cont[20]     ; reset_delay:u_reset_delay|cont[11]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.135      ;
; 0.916 ; reset_delay:u_reset_delay|cont[20]     ; reset_delay:u_reset_delay|cont[12]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.135      ;
; 0.916 ; reset_delay:u_reset_delay|cont[20]     ; reset_delay:u_reset_delay|cont[13]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.135      ;
; 0.916 ; reset_delay:u_reset_delay|cont[20]     ; reset_delay:u_reset_delay|cont[14]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.135      ;
; 0.916 ; reset_delay:u_reset_delay|cont[20]     ; reset_delay:u_reset_delay|cont[15]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.135      ;
; 0.916 ; reset_delay:u_reset_delay|cont[20]     ; reset_delay:u_reset_delay|cont[16]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.135      ;
; 0.916 ; reset_delay:u_reset_delay|cont[20]     ; reset_delay:u_reset_delay|cont[17]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.135      ;
+-------+----------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                     ;
+-------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                  ; To Node                                                                    ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 0.358 ; spi_ee_config:u_spi_ee_config|high_byte                                    ; spi_ee_config:u_spi_ee_config|high_byte                                    ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; spi_ee_config:u_spi_ee_config|clear_status                                 ; spi_ee_config:u_spi_ee_config|clear_status                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; spi_ee_config:u_spi_ee_config|read_ready                                   ; spi_ee_config:u_spi_ee_config|read_ready                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; spi_ee_config:u_spi_ee_config|spi_go                                       ; spi_ee_config:u_spi_ee_config|spi_go                                       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
; 0.361 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.580      ;
; 0.373 ; spi_ee_config:u_spi_ee_config|clear_status_d[1]                            ; spi_ee_config:u_spi_ee_config|clear_status_d[2]                            ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.593      ;
; 0.373 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[4] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[5] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.592      ;
; 0.373 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[7] ; spi_ee_config:u_spi_ee_config|low_byte_data[7]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.592      ;
; 0.374 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[2] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[3] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
; 0.374 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[3] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[4] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
; 0.380 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[6] ; spi_ee_config:u_spi_ee_config|low_byte_data[6]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.599      ;
; 0.382 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[6] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[7] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.601      ;
; 0.388 ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.608      ;
; 0.394 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[1] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[2] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.613      ;
; 0.395 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[0] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[1] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.614      ;
; 0.418 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.637      ;
; 0.421 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.640      ;
; 0.423 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[3] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.642      ;
; 0.424 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.643      ;
; 0.507 ; spi_ee_config:u_spi_ee_config|high_byte                                    ; spi_ee_config:u_spi_ee_config|p2s_data[8]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.726      ;
; 0.508 ; spi_ee_config:u_spi_ee_config|high_byte                                    ; spi_ee_config:u_spi_ee_config|p2s_data[9]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.727      ;
; 0.517 ; spi_ee_config:u_spi_ee_config|clear_status                                 ; spi_ee_config:u_spi_ee_config|clear_status_d[0]                            ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.736      ;
; 0.522 ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.741      ;
; 0.523 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[5] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[6] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.742      ;
; 0.524 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[5] ; spi_ee_config:u_spi_ee_config|low_byte_data[5]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.743      ;
; 0.524 ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.743      ;
; 0.547 ; spi_ee_config:u_spi_ee_config|high_byte                                    ; spi_ee_config:u_spi_ee_config|high_byte_d                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.766      ;
; 0.548 ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.768      ;
; 0.548 ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.768      ;
; 0.549 ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.769      ;
; 0.549 ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.769      ;
; 0.549 ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.769      ;
; 0.550 ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.770      ;
; 0.551 ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.771      ;
; 0.552 ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.772      ;
; 0.552 ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.772      ;
; 0.553 ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.773      ;
; 0.553 ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.773      ;
; 0.554 ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.774      ;
; 0.554 ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.774      ;
; 0.562 ; spi_ee_config:u_spi_ee_config|read_back                                    ; spi_ee_config:u_spi_ee_config|read_back_d                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.781      ;
; 0.568 ; spi_ee_config:u_spi_ee_config|read_ready                                   ; spi_ee_config:u_spi_ee_config|p2s_data[9]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.787      ;
; 0.570 ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.790      ;
; 0.572 ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.791      ;
; 0.578 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.797      ;
; 0.596 ; spi_ee_config:u_spi_ee_config|read_back                                    ; spi_ee_config:u_spi_ee_config|high_byte                                    ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.815      ;
; 0.598 ; spi_ee_config:u_spi_ee_config|spi_go                                       ; spi_ee_config:u_spi_ee_config|read_back                                    ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.817      ;
; 0.600 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.819      ;
; 0.601 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.820      ;
; 0.611 ; spi_ee_config:u_spi_ee_config|read_back                                    ; spi_ee_config:u_spi_ee_config|clear_status                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.830      ;
; 0.695 ; spi_ee_config:u_spi_ee_config|read_ready                                   ; spi_ee_config:u_spi_ee_config|spi_go                                       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.914      ;
; 0.749 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.968      ;
; 0.814 ; spi_ee_config:u_spi_ee_config|high_byte                                    ; spi_ee_config:u_spi_ee_config|spi_go                                       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.033      ;
; 0.820 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[3] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.039      ;
; 0.823 ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.043      ;
; 0.823 ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.043      ;
; 0.823 ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.043      ;
; 0.824 ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.044      ;
; 0.824 ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.044      ;
; 0.825 ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.045      ;
; 0.826 ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.046      ;
; 0.826 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.045      ;
; 0.833 ; spi_ee_config:u_spi_ee_config|low_byte_data[7]                             ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.087      ; 1.077      ;
; 0.837 ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.057      ;
; 0.838 ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.058      ;
; 0.839 ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.059      ;
; 0.839 ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.059      ;
; 0.840 ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.060      ;
; 0.840 ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.060      ;
; 0.840 ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.060      ;
; 0.841 ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.061      ;
; 0.841 ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.061      ;
; 0.841 ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.061      ;
; 0.842 ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.062      ;
; 0.842 ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.062      ;
; 0.843 ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.063      ;
; 0.843 ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.063      ;
; 0.850 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 1.072      ;
; 0.851 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[1]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 1.073      ;
; 0.851 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[6]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 1.073      ;
; 0.853 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 1.075      ;
; 0.853 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 1.075      ;
; 0.854 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[2]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 1.076      ;
; 0.855 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 1.077      ;
; 0.858 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 1.080      ;
; 0.859 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[1] ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.087      ; 1.103      ;
; 0.861 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 1.083      ;
; 0.862 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 1.084      ;
; 0.862 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 1.084      ;
; 0.863 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[0] ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.087      ; 1.107      ;
; 0.864 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[3]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 1.086      ;
; 0.869 ; spi_ee_config:u_spi_ee_config|low_byte_data[6]                             ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.087      ; 1.113      ;
; 0.875 ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.094      ;
+-------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                              ;
+--------+--------------------------------+----------------------------------------------------------------------------+--------------+------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                      ; To Node                                                                    ; Launch Clock ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------+----------------------------------------------------------------------------+--------------+------------------------------------------------------+--------------+------------+------------+
; 15.083 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.350     ; 2.512      ;
; 15.083 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.350     ; 2.512      ;
; 15.083 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[3] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.350     ; 2.512      ;
; 15.083 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.350     ; 2.512      ;
; 15.083 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.350     ; 2.512      ;
; 15.083 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.350     ; 2.512      ;
; 15.083 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.350     ; 2.512      ;
; 15.083 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.350     ; 2.512      ;
; 15.083 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.350     ; 2.512      ;
; 15.371 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[1]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.352     ; 2.222      ;
; 15.371 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[2]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.352     ; 2.222      ;
; 15.928 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.670      ;
; 15.928 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.670      ;
; 15.928 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.670      ;
; 15.928 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.670      ;
; 15.928 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.670      ;
; 15.928 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.670      ;
; 15.928 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.670      ;
; 15.928 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.670      ;
; 15.928 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.670      ;
; 15.928 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.670      ;
; 15.928 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.670      ;
; 15.928 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.670      ;
; 15.928 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.670      ;
; 15.928 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.670      ;
; 15.928 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.670      ;
; 15.937 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_back                                    ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.661      ;
; 15.937 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|high_byte                                    ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.661      ;
; 15.937 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.661      ;
; 15.937 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[0]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.661      ;
; 15.937 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[3]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.661      ;
; 15.937 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_go                                       ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.661      ;
; 15.937 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_back_d                                  ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.661      ;
; 15.937 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|high_byte_d                                  ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.347     ; 1.661      ;
+--------+--------------------------------+----------------------------------------------------------------------------+--------------+------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'CLOCK_50'                                                                                                             ;
+--------+--------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                      ; To Node                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; 17.330 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[19] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 2.599      ;
; 17.330 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[21] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 2.599      ;
; 17.330 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 2.599      ;
; 17.330 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 2.599      ;
; 17.587 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.065     ; 2.343      ;
; 18.009 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.068     ; 1.918      ;
; 18.009 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.068     ; 1.918      ;
; 18.009 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.068     ; 1.918      ;
; 18.009 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.068     ; 1.918      ;
; 18.033 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 1.896      ;
; 18.033 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 1.896      ;
; 18.033 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 1.896      ;
; 18.033 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 1.896      ;
; 18.033 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 1.896      ;
; 18.033 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 1.896      ;
; 18.033 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 1.896      ;
; 18.033 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 1.896      ;
; 18.033 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 1.896      ;
; 18.033 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 1.896      ;
; 18.033 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 1.896      ;
; 18.033 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 1.896      ;
; 18.033 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 1.896      ;
; 18.033 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 1.896      ;
; 18.033 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 1.896      ;
+--------+--------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'CLOCK_50'                                                                                                             ;
+-------+--------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                      ; To Node                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; 1.509 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[2]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.057      ; 1.723      ;
; 1.509 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[3]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.057      ; 1.723      ;
; 1.509 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[5]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.057      ; 1.723      ;
; 1.509 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[8]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.057      ; 1.723      ;
; 1.509 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[9]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.057      ; 1.723      ;
; 1.509 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[10] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.057      ; 1.723      ;
; 1.509 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[11] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.057      ; 1.723      ;
; 1.509 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.057      ; 1.723      ;
; 1.509 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[13] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.057      ; 1.723      ;
; 1.509 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.057      ; 1.723      ;
; 1.509 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.057      ; 1.723      ;
; 1.509 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.057      ; 1.723      ;
; 1.509 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.057      ; 1.723      ;
; 1.509 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.057      ; 1.723      ;
; 1.509 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[0]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.057      ; 1.723      ;
; 1.527 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[1]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.740      ;
; 1.527 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[4]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.740      ;
; 1.527 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[6]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.740      ;
; 1.527 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[7]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.740      ;
; 1.966 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.059      ; 2.182      ;
; 2.211 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[19] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.426      ;
; 2.211 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[21] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.426      ;
; 2.211 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.426      ;
; 2.211 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.426      ;
+-------+--------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                              ;
+-------+--------------------------------+----------------------------------------------------------------------------+--------------+------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                      ; To Node                                                                    ; Launch Clock ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------+----------------------------------------------------------------------------+--------------+------------------------------------------------------+--------------+------------+------------+
; 3.110 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_back                                    ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.860     ; 1.507      ;
; 3.110 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|high_byte                                    ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.860     ; 1.507      ;
; 3.110 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.860     ; 1.507      ;
; 3.110 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[0]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.860     ; 1.507      ;
; 3.110 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[3]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.860     ; 1.507      ;
; 3.110 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_go                                       ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.860     ; 1.507      ;
; 3.110 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_back_d                                  ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.860     ; 1.507      ;
; 3.110 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|high_byte_d                                  ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.860     ; 1.507      ;
; 3.122 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.859     ; 1.520      ;
; 3.122 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.859     ; 1.520      ;
; 3.122 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.859     ; 1.520      ;
; 3.122 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.859     ; 1.520      ;
; 3.122 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.859     ; 1.520      ;
; 3.122 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.859     ; 1.520      ;
; 3.122 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.859     ; 1.520      ;
; 3.122 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.859     ; 1.520      ;
; 3.122 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.859     ; 1.520      ;
; 3.122 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.859     ; 1.520      ;
; 3.122 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.859     ; 1.520      ;
; 3.122 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.859     ; 1.520      ;
; 3.122 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.859     ; 1.520      ;
; 3.122 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.859     ; 1.520      ;
; 3.122 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.859     ; 1.520      ;
; 3.649 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[1]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.864     ; 2.042      ;
; 3.649 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[2]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.864     ; 2.042      ;
; 3.927 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.863     ; 2.321      ;
; 3.927 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.863     ; 2.321      ;
; 3.927 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[3] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.863     ; 2.321      ;
; 3.927 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.863     ; 2.321      ;
; 3.927 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.863     ; 2.321      ;
; 3.927 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.863     ; 2.321      ;
; 3.927 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.863     ; 2.321      ;
; 3.927 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.863     ; 2.321      ;
; 3.927 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.863     ; 2.321      ;
+-------+--------------------------------+----------------------------------------------------------------------------+--------------+------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'                                                                                            ;
+-------+--------------+----------------+-----------------+----------+------------+----------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                         ;
+-------+--------------+----------------+-----------------+----------+------------+----------------------------------------------------------------+
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[0]                          ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[10]                         ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[11]                         ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[12]                         ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[13]                         ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[14]                         ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[16]                         ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[17]                         ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[18]                         ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[20]                         ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[2]                          ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[3]                          ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[5]                          ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[8]                          ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[9]                          ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_d[0]                              ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[0]                              ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[10]                             ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[1]                              ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[2]                              ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[3]                              ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[4]                              ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[5]                              ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[6]                              ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[7]                              ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[8]                              ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[9]                              ;
; 9.595 ; 9.779        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|oRST                                 ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[15]                         ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[1]                          ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[4]                          ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[6]                          ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[7]                          ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_d[1]                              ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[11]                             ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[12]                             ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[13]                             ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[14]                             ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[15]                             ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[16]                             ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[17]                             ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[18]                             ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[19]                             ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[20]                             ;
; 9.597 ; 9.781        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[19]                         ;
; 9.597 ; 9.781        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[21]                         ;
; 9.597 ; 9.781        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[22]                         ;
; 9.597 ; 9.781        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[23]                         ;
; 9.747 ; 9.747        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; CLOCK_50~input|o                                               ;
; 9.747 ; 9.747        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0]           ;
; 9.747 ; 9.747        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[1]           ;
; 9.747 ; 9.747        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|observablevcoout ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[0]|clk                                 ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[10]|clk                                ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[11]|clk                                ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[12]|clk                                ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[13]|clk                                ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[14]|clk                                ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[16]|clk                                ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[17]|clk                                ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[18]|clk                                ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[20]|clk                                ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[2]|clk                                 ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[3]|clk                                 ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[5]|clk                                 ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[8]|clk                                 ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[9]|clk                                 ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_d[0]|clk                                     ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[0]|clk                                      ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[10]|clk                                     ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[1]|clk                                      ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[2]|clk                                      ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[3]|clk                                      ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[4]|clk                                      ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[5]|clk                                      ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[6]|clk                                      ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[7]|clk                                      ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[8]|clk                                      ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[9]|clk                                      ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|oRST|clk                                         ;
; 9.758 ; 9.758        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[15]|clk                                ;
; 9.758 ; 9.758        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[1]|clk                                 ;
; 9.758 ; 9.758        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[4]|clk                                 ;
; 9.758 ; 9.758        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[6]|clk                                 ;
; 9.758 ; 9.758        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[7]|clk                                 ;
; 9.758 ; 9.758        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_d[1]|clk                                     ;
; 9.758 ; 9.758        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[11]|clk                                     ;
; 9.758 ; 9.758        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[12]|clk                                     ;
; 9.758 ; 9.758        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[13]|clk                                     ;
; 9.758 ; 9.758        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[14]|clk                                     ;
; 9.758 ; 9.758        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[15]|clk                                     ;
; 9.758 ; 9.758        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[16]|clk                                     ;
; 9.758 ; 9.758        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[17]|clk                                     ;
; 9.758 ; 9.758        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[18]|clk                                     ;
; 9.758 ; 9.758        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[19]|clk                                     ;
; 9.758 ; 9.758        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[20]|clk                                     ;
; 9.759 ; 9.759        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[19]|clk                                ;
; 9.759 ; 9.759        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[21]|clk                                ;
; 9.759 ; 9.759        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[22]|clk                                ;
; 9.759 ; 9.759        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[23]|clk                                ;
+-------+--------------+----------------+-----------------+----------+------------+----------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                           ;
+---------+--------------+----------------+------------------+------------------------------------------------------+------------+----------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock                                                ; Clock Edge ; Target                                                                     ;
+---------+--------------+----------------+------------------+------------------------------------------------------+------------+----------------------------------------------------------------------------+
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status_d[1]                            ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status_d[2]                            ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|low_byte_data[5]                             ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|low_byte_data[6]                             ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|low_byte_data[7]                             ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_L[5]                                   ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[1]                                  ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[2]                                  ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[3]                                  ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[6]                                  ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[0] ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[1] ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[2] ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[3] ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[4] ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[5] ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[6] ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[7] ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status                                 ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status_d[0]                            ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status_d[3]                            ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|high_byte                                    ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|high_byte_d                                  ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[8]                                  ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[9]                                  ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_back                                    ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_back_d                                  ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_ready                                   ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[3] ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ;
; 249.749 ; 249.965      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_go                                       ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status                                 ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status_d[0]                            ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status_d[3]                            ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|high_byte                                    ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|high_byte_d                                  ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|low_byte_data[5]                             ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|low_byte_data[6]                             ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|low_byte_data[7]                             ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[1]                                  ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[2]                                  ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[3]                                  ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[6]                                  ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[8]                                  ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[9]                                  ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_back                                    ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_back_d                                  ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ;
; 249.850 ; 250.034      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ;
+---------+--------------+----------------+------------------+------------------------------------------------------+------------+----------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                         ;
+--------------+------------+----------+----------+------------+------------------------------------------------------+
; Data Port    ; Clock Port ; Rise     ; Fall     ; Clock Edge ; Clock Reference                                      ;
+--------------+------------+----------+----------+------------+------------------------------------------------------+
; G_SENSOR_INT ; CLOCK_50   ; 0.360    ; 0.533    ; Rise       ; CLOCK_50                                             ;
; G_SENSOR_INT ; CLOCK_50   ; -195.523 ; -195.437 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SDAT     ; CLOCK_50   ; -196.094 ; -195.565 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
+--------------+------------+----------+----------+------------+------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                        ;
+--------------+------------+---------+---------+------------+------------------------------------------------------+
; Data Port    ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                      ;
+--------------+------------+---------+---------+------------+------------------------------------------------------+
; G_SENSOR_INT ; CLOCK_50   ; -0.056  ; -0.232  ; Rise       ; CLOCK_50                                             ;
; G_SENSOR_INT ; CLOCK_50   ; 196.979 ; 196.928 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SDAT     ; CLOCK_50   ; 196.786 ; 196.280 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
+--------------+------------+---------+---------+------------+------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                              ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+
; Data Port     ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                      ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+
; LED[*]        ; CLOCK_50   ; 11.650  ; 11.872  ; Rise       ; CLOCK_50                                             ;
;  LED[0]       ; CLOCK_50   ; 8.480   ; 8.381   ; Rise       ; CLOCK_50                                             ;
;  LED[1]       ; CLOCK_50   ; 8.953   ; 8.863   ; Rise       ; CLOCK_50                                             ;
;  LED[2]       ; CLOCK_50   ; 8.143   ; 8.140   ; Rise       ; CLOCK_50                                             ;
;  LED[3]       ; CLOCK_50   ; 9.162   ; 8.984   ; Rise       ; CLOCK_50                                             ;
;  LED[4]       ; CLOCK_50   ; 9.538   ; 9.380   ; Rise       ; CLOCK_50                                             ;
;  LED[5]       ; CLOCK_50   ; 9.302   ; 9.619   ; Rise       ; CLOCK_50                                             ;
;  LED[6]       ; CLOCK_50   ; 8.870   ; 8.850   ; Rise       ; CLOCK_50                                             ;
;  LED[7]       ; CLOCK_50   ; 11.650  ; 11.872  ; Rise       ; CLOCK_50                                             ;
; G_SENSOR_CS_N ; CLOCK_50   ; 204.141 ; 204.127 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SCLK      ; CLOCK_50   ; 205.179 ; 205.000 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SDAT      ; CLOCK_50   ; 207.585 ; 207.548 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; LED[*]        ; CLOCK_50   ; 210.518 ; 210.826 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[0]       ; CLOCK_50   ; 206.798 ; 206.800 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[1]       ; CLOCK_50   ; 207.528 ; 207.415 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[2]       ; CLOCK_50   ; 207.155 ; 207.133 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[3]       ; CLOCK_50   ; 207.732 ; 207.563 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[4]       ; CLOCK_50   ; 208.108 ; 207.959 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[5]       ; CLOCK_50   ; 208.840 ; 209.156 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[6]       ; CLOCK_50   ; 207.738 ; 207.804 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[7]       ; CLOCK_50   ; 210.518 ; 210.826 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SCLK      ; CLOCK_50   ; 170.725 ;         ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[1] ;
; I2C_SCLK      ; CLOCK_50   ;         ; 170.590 ; Fall       ; u_spipll|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                      ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+
; Data Port     ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                      ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+
; LED[*]        ; CLOCK_50   ; 7.573   ; 7.483   ; Rise       ; CLOCK_50                                             ;
;  LED[0]       ; CLOCK_50   ; 7.893   ; 7.818   ; Rise       ; CLOCK_50                                             ;
;  LED[1]       ; CLOCK_50   ; 7.874   ; 7.780   ; Rise       ; CLOCK_50                                             ;
;  LED[2]       ; CLOCK_50   ; 7.573   ; 7.483   ; Rise       ; CLOCK_50                                             ;
;  LED[3]       ; CLOCK_50   ; 7.982   ; 7.829   ; Rise       ; CLOCK_50                                             ;
;  LED[4]       ; CLOCK_50   ; 8.340   ; 8.206   ; Rise       ; CLOCK_50                                             ;
;  LED[5]       ; CLOCK_50   ; 8.884   ; 9.119   ; Rise       ; CLOCK_50                                             ;
;  LED[6]       ; CLOCK_50   ; 7.577   ; 7.624   ; Rise       ; CLOCK_50                                             ;
;  LED[7]       ; CLOCK_50   ; 10.659  ; 10.936  ; Rise       ; CLOCK_50                                             ;
; G_SENSOR_CS_N ; CLOCK_50   ; 203.612 ; 203.602 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SCLK      ; CLOCK_50   ; 204.574 ; 204.411 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SDAT      ; CLOCK_50   ; 204.230 ; 204.116 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; LED[*]        ; CLOCK_50   ; 204.376 ; 204.348 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[0]       ; CLOCK_50   ; 205.272 ; 205.234 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[1]       ; CLOCK_50   ; 205.726 ; 205.751 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[2]       ; CLOCK_50   ; 204.376 ; 204.348 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[3]       ; CLOCK_50   ; 205.076 ; 205.038 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[4]       ; CLOCK_50   ; 205.313 ; 205.174 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[5]       ; CLOCK_50   ; 206.214 ; 206.406 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[6]       ; CLOCK_50   ; 204.976 ; 204.919 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[7]       ; CLOCK_50   ; 208.157 ; 208.384 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SCLK      ; CLOCK_50   ; 170.218 ;         ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[1] ;
; I2C_SCLK      ; CLOCK_50   ;         ; 170.084 ; Fall       ; u_spipll|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+


+----------------------------------------------------------------+
; Propagation Delay                                              ;
+--------------+-------------+--------+--------+--------+--------+
; Input Port   ; Output Port ; RR     ; RF     ; FR     ; FF     ;
+--------------+-------------+--------+--------+--------+--------+
; G_SENSOR_INT ; LED[0]      ; 7.474  ; 8.106  ; 8.331  ; 7.597  ;
; G_SENSOR_INT ; LED[1]      ; 9.115  ; 8.787  ; 9.009  ; 9.196  ;
; G_SENSOR_INT ; LED[2]      ; 8.662  ; 8.640  ; 8.812  ; 8.822  ;
; G_SENSOR_INT ; LED[3]      ; 9.239  ; 8.792  ; 8.942  ; 9.302  ;
; G_SENSOR_INT ; LED[4]      ; 9.615  ; 9.191  ; 9.320  ; 9.698  ;
; G_SENSOR_INT ; LED[5]      ; 10.347 ; 10.663 ; 10.497 ; 10.845 ;
; G_SENSOR_INT ; LED[6]      ; 8.193  ; 9.311  ; 9.477  ; 8.244  ;
; G_SENSOR_INT ; LED[7]      ; 10.389 ; 12.333 ; 12.257 ; 10.791 ;
+--------------+-------------+--------+--------+--------+--------+


+----------------------------------------------------------------+
; Minimum Propagation Delay                                      ;
+--------------+-------------+--------+--------+--------+--------+
; Input Port   ; Output Port ; RR     ; RF     ; FR     ; FF     ;
+--------------+-------------+--------+--------+--------+--------+
; G_SENSOR_INT ; LED[0]      ; 7.222  ; 7.671  ; 7.881  ; 7.345  ;
; G_SENSOR_INT ; LED[1]      ; 8.367  ; 7.810  ; 8.041  ; 8.469  ;
; G_SENSOR_INT ; LED[2]      ; 7.373  ; 7.229  ; 7.443  ; 7.556  ;
; G_SENSOR_INT ; LED[3]      ; 7.403  ; 7.325  ; 7.594  ; 7.507  ;
; G_SENSOR_INT ; LED[4]      ; 7.768  ; 7.712  ; 7.959  ; 7.894  ;
; G_SENSOR_INT ; LED[5]      ; 9.028  ; 9.241  ; 9.098  ; 9.568  ;
; G_SENSOR_INT ; LED[6]      ; 7.540  ; 6.970  ; 7.201  ; 7.663  ;
; G_SENSOR_INT ; LED[7]      ; 10.087 ; 10.821 ; 10.746 ; 10.495 ;
+--------------+-------------+--------+--------+--------+--------+


+----------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                            ;
+-----------+------------+---------+---------+------------+------------------------------------------------------+
; Data Port ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                      ;
+-----------+------------+---------+---------+------------+------------------------------------------------------+
; I2C_SDAT  ; CLOCK_50   ; 205.287 ; 205.165 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+---------+---------+------------+------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                    ;
+-----------+------------+---------+---------+------------+------------------------------------------------------+
; Data Port ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                      ;
+-----------+------------+---------+---------+------------+------------------------------------------------------+
; I2C_SDAT  ; CLOCK_50   ; 204.181 ; 204.059 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+---------+---------+------------+------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                               ;
+-----------+------------+-----------+-----------+------------+------------------------------------------------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                      ;
+-----------+------------+-----------+-----------+------------+------------------------------------------------------+
; I2C_SDAT  ; CLOCK_50   ; 205.085   ; 205.207   ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-----------+-----------+------------+------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                       ;
+-----------+------------+-----------+-----------+------------+------------------------------------------------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                      ;
+-----------+------------+-----------+-----------+------------+------------------------------------------------------+
; I2C_SDAT  ; CLOCK_50   ; 204.088   ; 204.210   ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-----------+-----------+------------+------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                                                   ;
+------------+-----------------+------------------------------------------------------+---------------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                           ; Note                                                          ;
+------------+-----------------+------------------------------------------------------+---------------------------------------------------------------+
; 294.46 MHz ; 250.0 MHz       ; CLOCK_50                                             ; limit due to minimum period restriction (max I/O toggle rate) ;
; 300.03 MHz ; 300.03 MHz      ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;                                                               ;
+------------+-----------------+------------------------------------------------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+-------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                            ;
+------------------------------------------------------+--------+---------------+
; Clock                                                ; Slack  ; End Point TNS ;
+------------------------------------------------------+--------+---------------+
; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 15.596 ; 0.000         ;
; CLOCK_50                                             ; 16.604 ; 0.000         ;
+------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                            ;
+------------------------------------------------------+-------+---------------+
; Clock                                                ; Slack ; End Point TNS ;
+------------------------------------------------------+-------+---------------+
; CLOCK_50                                             ; 0.312 ; 0.000         ;
; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.312 ; 0.000         ;
+------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                         ;
+------------------------------------------------------+--------+---------------+
; Clock                                                ; Slack  ; End Point TNS ;
+------------------------------------------------------+--------+---------------+
; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 15.632 ; 0.000         ;
; CLOCK_50                                             ; 17.585 ; 0.000         ;
+------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                         ;
+------------------------------------------------------+-------+---------------+
; Clock                                                ; Slack ; End Point TNS ;
+------------------------------------------------------+-------+---------------+
; CLOCK_50                                             ; 1.386 ; 0.000         ;
; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 2.758 ; 0.000         ;
+------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                               ;
+------------------------------------------------------+---------+---------------+
; Clock                                                ; Slack   ; End Point TNS ;
+------------------------------------------------------+---------+---------------+
; CLOCK_50                                             ; 9.596   ; 0.000         ;
; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 249.744 ; 0.000         ;
+------------------------------------------------------+---------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                       ;
+---------+--------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                  ; To Node                                                                    ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+---------+--------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 15.596  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 2.295      ;
; 15.596  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 2.295      ;
; 15.596  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 2.295      ;
; 15.596  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 2.295      ;
; 15.596  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 2.295      ;
; 15.629  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.046     ; 2.270      ;
; 15.629  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.046     ; 2.270      ;
; 15.629  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.046     ; 2.270      ;
; 15.629  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.046     ; 2.270      ;
; 15.629  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|oDATA_L[5]                                   ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.046     ; 2.270      ;
; 15.792  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|low_byte_data[6]                             ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 2.099      ;
; 15.792  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|low_byte_data[7]                             ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 2.099      ;
; 15.792  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|low_byte_data[5]                             ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 2.099      ;
; 15.817  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[8]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 2.074      ;
; 15.817  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[9]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 2.074      ;
; 16.100  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.791      ;
; 16.100  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.791      ;
; 16.100  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.791      ;
; 16.100  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[1]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.791      ;
; 16.100  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[3]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.791      ;
; 16.100  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[2]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.791      ;
; 16.100  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[6]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.791      ;
; 16.234  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[0] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.657      ;
; 16.234  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[1] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.657      ;
; 16.234  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[2] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.657      ;
; 16.234  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[3] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.657      ;
; 16.234  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[4] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.657      ;
; 16.234  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[5] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.657      ;
; 16.234  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[6] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.657      ;
; 16.234  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[7] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.657      ;
; 16.725  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|read_ready                                   ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.166      ;
; 496.667 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.276      ;
; 496.667 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.276      ;
; 496.667 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.276      ;
; 496.667 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.276      ;
; 496.667 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.276      ;
; 496.689 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.254      ;
; 496.689 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.254      ;
; 496.689 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.254      ;
; 496.689 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[1]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.254      ;
; 496.689 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[3]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.254      ;
; 496.689 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[2]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.254      ;
; 496.689 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[6]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.254      ;
; 496.689 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.254      ;
; 496.689 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.254      ;
; 496.689 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.254      ;
; 496.689 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.254      ;
; 496.689 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.254      ;
; 496.711 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.232      ;
; 496.711 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.232      ;
; 496.711 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.232      ;
; 496.711 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[1]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.232      ;
; 496.711 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[3]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.232      ;
; 496.711 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[2]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.232      ;
; 496.711 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[6]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.232      ;
; 496.754 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.058     ; 3.183      ;
; 496.754 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.058     ; 3.183      ;
; 496.754 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.058     ; 3.183      ;
; 496.754 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.058     ; 3.183      ;
; 496.754 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|oDATA_L[5]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.058     ; 3.183      ;
; 496.770 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.173      ;
; 496.770 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.173      ;
; 496.770 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.173      ;
; 496.770 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.173      ;
; 496.770 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.173      ;
; 496.776 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.058     ; 3.161      ;
; 496.776 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.058     ; 3.161      ;
; 496.776 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.058     ; 3.161      ;
; 496.776 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.058     ; 3.161      ;
; 496.776 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|oDATA_L[5]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.058     ; 3.161      ;
; 496.792 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.151      ;
; 496.792 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.151      ;
; 496.792 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.151      ;
; 496.792 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[1]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.151      ;
; 496.792 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[3]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.151      ;
; 496.792 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[2]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.151      ;
; 496.792 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[6]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.151      ;
; 496.857 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.058     ; 3.080      ;
; 496.857 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.058     ; 3.080      ;
; 496.857 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.058     ; 3.080      ;
; 496.857 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.058     ; 3.080      ;
; 496.857 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|oDATA_L[5]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.058     ; 3.080      ;
; 496.888 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[8]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.055      ;
; 496.888 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[9]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.055      ;
; 496.906 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.037      ;
; 496.906 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.037      ;
; 496.906 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.037      ;
; 496.906 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.037      ;
; 496.906 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.037      ;
; 496.910 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[8]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.033      ;
; 496.910 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[9]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.033      ;
; 496.911 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|low_byte_data[6]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.032      ;
; 496.911 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|low_byte_data[7]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.032      ;
; 496.911 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|low_byte_data[5]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.032      ;
; 496.928 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.015      ;
; 496.928 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.015      ;
; 496.928 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.015      ;
; 496.928 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[1]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.015      ;
; 496.928 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[3]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.015      ;
; 496.928 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[2]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.052     ; 3.015      ;
+---------+--------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'CLOCK_50'                                                                                                                         ;
+--------+----------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                              ; To Node                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; 16.604 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 3.336      ;
; 16.643 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 3.297      ;
; 16.655 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 3.287      ;
; 16.683 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 3.257      ;
; 16.690 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 3.250      ;
; 16.738 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 3.202      ;
; 16.827 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 3.114      ;
; 16.870 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 3.070      ;
; 16.898 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 3.043      ;
; 16.918 ; led_driver:u_led_driver|int2_count[9]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 3.022      ;
; 16.921 ; led_driver:u_led_driver|int2_count[4]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 3.021      ;
; 16.940 ; led_driver:u_led_driver|int2_count[12] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 3.000      ;
; 16.941 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.999      ;
; 16.949 ; led_driver:u_led_driver|int2_count[7]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 2.993      ;
; 16.979 ; led_driver:u_led_driver|int2_count[8]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.961      ;
; 16.983 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 2.958      ;
; 16.992 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.948      ;
; 16.995 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 2.948      ;
; 17.020 ; led_driver:u_led_driver|int2_count[6]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 2.922      ;
; 17.030 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 2.911      ;
; 17.031 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.909      ;
; 17.041 ; led_driver:u_led_driver|int2_count[11] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.899      ;
; 17.043 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 2.899      ;
; 17.044 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.896      ;
; 17.056 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 2.886      ;
; 17.071 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.869      ;
; 17.078 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 2.863      ;
; 17.078 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.862      ;
; 17.081 ; led_driver:u_led_driver|int2_count[10] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.859      ;
; 17.089 ; led_driver:u_led_driver|int2_count[17] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.851      ;
; 17.090 ; led_driver:u_led_driver|int2_count[14] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.850      ;
; 17.091 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.849      ;
; 17.098 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.842      ;
; 17.126 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.814      ;
; 17.137 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.803      ;
; 17.139 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.801      ;
; 17.141 ; led_driver:u_led_driver|int2_count[12] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 2.800      ;
; 17.149 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 2.793      ;
; 17.161 ; led_driver:u_led_driver|int2_count[4]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 2.782      ;
; 17.177 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.763      ;
; 17.184 ; led_driver:u_led_driver|int2_count[16] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.756      ;
; 17.184 ; led_driver:u_led_driver|int2_count[12] ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.756      ;
; 17.184 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.756      ;
; 17.192 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.748      ;
; 17.194 ; led_driver:u_led_driver|int2_count[8]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 2.747      ;
; 17.204 ; led_driver:u_led_driver|int2_count[4]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 2.738      ;
; 17.211 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.729      ;
; 17.215 ; led_driver:u_led_driver|int2_count[15] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.722      ;
; 17.225 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 2.718      ;
; 17.231 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.709      ;
; 17.232 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.708      ;
; 17.237 ; led_driver:u_led_driver|int2_count[8]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.703      ;
; 17.243 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 2.699      ;
; 17.250 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.690      ;
; 17.258 ; led_driver:u_led_driver|int2_count[9]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 2.683      ;
; 17.260 ; led_driver:u_led_driver|int2_count[6]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 2.683      ;
; 17.262 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 2.680      ;
; 17.271 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.669      ;
; 17.285 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[19] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 2.656      ;
; 17.288 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 2.653      ;
; 17.289 ; led_driver:u_led_driver|int2_count[7]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 2.654      ;
; 17.290 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.650      ;
; 17.296 ; led_driver:u_led_driver|int2_count[10] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 2.645      ;
; 17.296 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 2.647      ;
; 17.297 ; led_driver:u_led_driver|int2_count[14] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 2.644      ;
; 17.297 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.643      ;
; 17.301 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[21] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 2.640      ;
; 17.303 ; led_driver:u_led_driver|int2_count[6]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 2.639      ;
; 17.306 ; led_driver:u_led_driver|int2_count[9]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.634      ;
; 17.309 ; led_driver:u_led_driver|int2_count[4]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 2.633      ;
; 17.319 ; led_driver:u_led_driver|int2_count[9]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.621      ;
; 17.326 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.614      ;
; 17.326 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.614      ;
; 17.327 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 2.614      ;
; 17.328 ; led_driver:u_led_driver|int2_count[12] ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.612      ;
; 17.337 ; led_driver:u_led_driver|int2_count[7]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 2.605      ;
; 17.339 ; led_driver:u_led_driver|int2_count[10] ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.601      ;
; 17.339 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 2.604      ;
; 17.340 ; led_driver:u_led_driver|int2_count[14] ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.600      ;
; 17.345 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.595      ;
; 17.350 ; led_driver:u_led_driver|int2_count[20] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 2.591      ;
; 17.350 ; led_driver:u_led_driver|int2_count[7]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 2.592      ;
; 17.356 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[19] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 2.585      ;
; 17.359 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 2.584      ;
; 17.367 ; led_driver:u_led_driver|int2_count[8]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.573      ;
; 17.367 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 2.574      ;
; 17.371 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 2.574      ;
; 17.372 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.568      ;
; 17.372 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[21] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 2.569      ;
; 17.374 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 2.567      ;
; 17.381 ; led_driver:u_led_driver|int2_count[11] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 2.560      ;
; 17.386 ; led_driver:u_led_driver|int2_count[16] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 2.555      ;
; 17.396 ; reset_delay:u_reset_delay|cont[1]      ; reset_delay:u_reset_delay|cont[20]     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 2.547      ;
; 17.397 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.543      ;
; 17.400 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.540      ;
; 17.406 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 2.537      ;
; 17.408 ; led_driver:u_led_driver|int2_count[6]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 2.534      ;
; 17.411 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.529      ;
; 17.412 ; led_driver:u_led_driver|int2_count[9]  ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 2.528      ;
; 17.415 ; led_driver:u_led_driver|int2_count[4]  ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 2.527      ;
+--------+----------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'CLOCK_50'                                                                                                                         ;
+-------+----------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                              ; To Node                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.312 ; reset_delay:u_reset_delay|cont[20]     ; reset_delay:u_reset_delay|cont[20]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; led_driver:u_led_driver|int2_count[23] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.320 ; reset_delay:u_reset_delay|cont[0]      ; reset_delay:u_reset_delay|cont[0]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.519      ;
; 0.492 ; reset_delay:u_reset_delay|cont[8]      ; reset_delay:u_reset_delay|cont[8]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.691      ;
; 0.492 ; reset_delay:u_reset_delay|cont[10]     ; reset_delay:u_reset_delay|cont[10]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.691      ;
; 0.493 ; reset_delay:u_reset_delay|cont[6]      ; reset_delay:u_reset_delay|cont[6]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.692      ;
; 0.493 ; reset_delay:u_reset_delay|cont[14]     ; reset_delay:u_reset_delay|cont[14]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.692      ;
; 0.494 ; reset_delay:u_reset_delay|cont[16]     ; reset_delay:u_reset_delay|cont[16]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.693      ;
; 0.495 ; reset_delay:u_reset_delay|cont[12]     ; reset_delay:u_reset_delay|cont[12]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.694      ;
; 0.495 ; reset_delay:u_reset_delay|cont[17]     ; reset_delay:u_reset_delay|cont[17]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.694      ;
; 0.496 ; reset_delay:u_reset_delay|cont[2]      ; reset_delay:u_reset_delay|cont[2]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.695      ;
; 0.496 ; reset_delay:u_reset_delay|cont[4]      ; reset_delay:u_reset_delay|cont[4]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.695      ;
; 0.496 ; reset_delay:u_reset_delay|cont[11]     ; reset_delay:u_reset_delay|cont[11]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.695      ;
; 0.497 ; reset_delay:u_reset_delay|cont[9]      ; reset_delay:u_reset_delay|cont[9]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.696      ;
; 0.497 ; reset_delay:u_reset_delay|cont[13]     ; reset_delay:u_reset_delay|cont[13]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.696      ;
; 0.497 ; reset_delay:u_reset_delay|cont[18]     ; reset_delay:u_reset_delay|cont[18]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.696      ;
; 0.498 ; reset_delay:u_reset_delay|cont[3]      ; reset_delay:u_reset_delay|cont[3]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.697      ;
; 0.498 ; reset_delay:u_reset_delay|cont[5]      ; reset_delay:u_reset_delay|cont[5]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.697      ;
; 0.498 ; reset_delay:u_reset_delay|cont[7]      ; reset_delay:u_reset_delay|cont[7]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.697      ;
; 0.499 ; reset_delay:u_reset_delay|cont[15]     ; reset_delay:u_reset_delay|cont[15]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.698      ;
; 0.499 ; reset_delay:u_reset_delay|cont[19]     ; reset_delay:u_reset_delay|cont[19]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.698      ;
; 0.508 ; reset_delay:u_reset_delay|cont[0]      ; reset_delay:u_reset_delay|cont[1]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.707      ;
; 0.531 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.730      ;
; 0.598 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[11] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.052      ; 0.794      ;
; 0.612 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.052      ; 0.808      ;
; 0.613 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[3]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.052      ; 0.809      ;
; 0.620 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[0]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.052      ; 0.816      ;
; 0.621 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[2]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.052      ; 0.817      ;
; 0.638 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[21] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 0.835      ;
; 0.638 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 0.835      ;
; 0.641 ; reset_delay:u_reset_delay|cont[1]      ; reset_delay:u_reset_delay|cont[1]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.840      ;
; 0.645 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[10] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.844      ;
; 0.646 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.845      ;
; 0.647 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[8]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.846      ;
; 0.647 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[9]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.846      ;
; 0.651 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[5]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.850      ;
; 0.651 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.850      ;
; 0.653 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[11] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.852      ;
; 0.654 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.853      ;
; 0.655 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.854      ;
; 0.656 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[13] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.855      ;
; 0.657 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.856      ;
; 0.658 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.857      ;
; 0.701 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 0.903      ;
; 0.711 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_d[1]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 0.913      ;
; 0.712 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[7]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 0.909      ;
; 0.714 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[19] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 0.911      ;
; 0.731 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 0.928      ;
; 0.733 ; reset_delay:u_reset_delay|cont[10]     ; reset_delay:u_reset_delay|cont[11]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 0.935      ;
; 0.736 ; reset_delay:u_reset_delay|cont[8]      ; reset_delay:u_reset_delay|cont[9]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.935      ;
; 0.737 ; reset_delay:u_reset_delay|cont[6]      ; reset_delay:u_reset_delay|cont[7]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.936      ;
; 0.737 ; reset_delay:u_reset_delay|cont[14]     ; reset_delay:u_reset_delay|cont[15]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.936      ;
; 0.738 ; reset_delay:u_reset_delay|cont[16]     ; reset_delay:u_reset_delay|cont[17]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.937      ;
; 0.740 ; reset_delay:u_reset_delay|cont[12]     ; reset_delay:u_reset_delay|cont[13]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.939      ;
; 0.741 ; reset_delay:u_reset_delay|cont[2]      ; reset_delay:u_reset_delay|cont[3]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.940      ;
; 0.741 ; reset_delay:u_reset_delay|cont[4]      ; reset_delay:u_reset_delay|cont[5]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.940      ;
; 0.742 ; reset_delay:u_reset_delay|cont[18]     ; reset_delay:u_reset_delay|cont[19]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.941      ;
; 0.743 ; reset_delay:u_reset_delay|cont[0]      ; reset_delay:u_reset_delay|cont[2]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.942      ;
; 0.744 ; reset_delay:u_reset_delay|cont[17]     ; reset_delay:u_reset_delay|cont[18]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.943      ;
; 0.745 ; reset_delay:u_reset_delay|cont[11]     ; reset_delay:u_reset_delay|cont[12]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.944      ;
; 0.746 ; reset_delay:u_reset_delay|cont[9]      ; reset_delay:u_reset_delay|cont[10]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.945      ;
; 0.746 ; reset_delay:u_reset_delay|cont[13]     ; reset_delay:u_reset_delay|cont[14]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.945      ;
; 0.747 ; reset_delay:u_reset_delay|cont[7]      ; reset_delay:u_reset_delay|cont[8]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.946      ;
; 0.747 ; reset_delay:u_reset_delay|cont[5]      ; reset_delay:u_reset_delay|cont[6]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.946      ;
; 0.747 ; reset_delay:u_reset_delay|cont[3]      ; reset_delay:u_reset_delay|cont[4]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.946      ;
; 0.748 ; reset_delay:u_reset_delay|cont[15]     ; reset_delay:u_reset_delay|cont[16]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.947      ;
; 0.750 ; reset_delay:u_reset_delay|cont[9]      ; reset_delay:u_reset_delay|cont[11]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 0.952      ;
; 0.750 ; reset_delay:u_reset_delay|cont[0]      ; reset_delay:u_reset_delay|cont[3]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.949      ;
; 0.751 ; reset_delay:u_reset_delay|cont[17]     ; reset_delay:u_reset_delay|cont[19]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.950      ;
; 0.752 ; reset_delay:u_reset_delay|cont[11]     ; reset_delay:u_reset_delay|cont[13]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.951      ;
; 0.753 ; reset_delay:u_reset_delay|cont[13]     ; reset_delay:u_reset_delay|cont[15]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.952      ;
; 0.754 ; reset_delay:u_reset_delay|cont[7]      ; reset_delay:u_reset_delay|cont[9]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.953      ;
; 0.754 ; reset_delay:u_reset_delay|cont[5]      ; reset_delay:u_reset_delay|cont[7]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.953      ;
; 0.754 ; reset_delay:u_reset_delay|cont[3]      ; reset_delay:u_reset_delay|cont[5]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.953      ;
; 0.755 ; reset_delay:u_reset_delay|cont[15]     ; reset_delay:u_reset_delay|cont[17]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.954      ;
; 0.761 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[1]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.959      ;
; 0.761 ; led_driver:u_led_driver|int2_count[22] ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.960      ;
; 0.763 ; led_driver:u_led_driver|int2_count[21] ; led_driver:u_led_driver|int2_count[21] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.962      ;
; 0.765 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.052      ; 0.961      ;
; 0.766 ; led_driver:u_led_driver|int2_count[4]  ; led_driver:u_led_driver|int2_count[4]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.964      ;
; 0.766 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[13] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.052      ; 0.962      ;
; 0.767 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.052      ; 0.963      ;
; 0.767 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.052      ; 0.963      ;
; 0.768 ; led_driver:u_led_driver|int2_count[6]  ; led_driver:u_led_driver|int2_count[6]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.966      ;
; 0.777 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.052      ; 0.973      ;
; 0.779 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[0]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.978      ;
; 0.780 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[2]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.979      ;
; 0.785 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.052      ; 0.981      ;
; 0.785 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[5]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.052      ; 0.981      ;
; 0.786 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[8]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.052      ; 0.982      ;
; 0.787 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[9]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.052      ; 0.983      ;
; 0.788 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[3]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.987      ;
; 0.788 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[10] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.052      ; 0.984      ;
; 0.822 ; reset_delay:u_reset_delay|cont[10]     ; reset_delay:u_reset_delay|cont[12]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 1.024      ;
; 0.825 ; reset_delay:u_reset_delay|cont[8]      ; reset_delay:u_reset_delay|cont[10]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 1.024      ;
; 0.826 ; reset_delay:u_reset_delay|cont[6]      ; reset_delay:u_reset_delay|cont[8]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 1.025      ;
; 0.826 ; reset_delay:u_reset_delay|cont[14]     ; reset_delay:u_reset_delay|cont[16]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 1.025      ;
; 0.827 ; reset_delay:u_reset_delay|cont[16]     ; reset_delay:u_reset_delay|cont[18]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 1.026      ;
; 0.829 ; reset_delay:u_reset_delay|cont[20]     ; reset_delay:u_reset_delay|cont[11]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 1.028      ;
; 0.829 ; reset_delay:u_reset_delay|cont[20]     ; reset_delay:u_reset_delay|cont[12]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 1.028      ;
+-------+----------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                      ;
+-------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                  ; To Node                                                                    ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 0.312 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.313 ; spi_ee_config:u_spi_ee_config|high_byte                                    ; spi_ee_config:u_spi_ee_config|high_byte                                    ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; spi_ee_config:u_spi_ee_config|clear_status                                 ; spi_ee_config:u_spi_ee_config|clear_status                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; spi_ee_config:u_spi_ee_config|read_ready                                   ; spi_ee_config:u_spi_ee_config|read_ready                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; spi_ee_config:u_spi_ee_config|spi_go                                       ; spi_ee_config:u_spi_ee_config|spi_go                                       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
; 0.320 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.519      ;
; 0.339 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[4] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[5] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.537      ;
; 0.340 ; spi_ee_config:u_spi_ee_config|clear_status_d[1]                            ; spi_ee_config:u_spi_ee_config|clear_status_d[2]                            ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.538      ;
; 0.340 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[3] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[4] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.538      ;
; 0.340 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[7] ; spi_ee_config:u_spi_ee_config|low_byte_data[7]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.538      ;
; 0.341 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[2] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[3] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.539      ;
; 0.346 ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.545      ;
; 0.346 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[6] ; spi_ee_config:u_spi_ee_config|low_byte_data[6]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.544      ;
; 0.348 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[6] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[7] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.546      ;
; 0.359 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[0] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[1] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.557      ;
; 0.359 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[1] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[2] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.557      ;
; 0.380 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.579      ;
; 0.382 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.581      ;
; 0.384 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[3] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.583      ;
; 0.385 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.584      ;
; 0.455 ; spi_ee_config:u_spi_ee_config|high_byte                                    ; spi_ee_config:u_spi_ee_config|p2s_data[8]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.653      ;
; 0.456 ; spi_ee_config:u_spi_ee_config|high_byte                                    ; spi_ee_config:u_spi_ee_config|p2s_data[9]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.654      ;
; 0.467 ; spi_ee_config:u_spi_ee_config|clear_status                                 ; spi_ee_config:u_spi_ee_config|clear_status_d[0]                            ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.665      ;
; 0.471 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[5] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[6] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.669      ;
; 0.473 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[5] ; spi_ee_config:u_spi_ee_config|low_byte_data[5]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.671      ;
; 0.479 ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.678      ;
; 0.481 ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.680      ;
; 0.490 ; spi_ee_config:u_spi_ee_config|high_byte                                    ; spi_ee_config:u_spi_ee_config|high_byte_d                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.688      ;
; 0.493 ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.692      ;
; 0.493 ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.692      ;
; 0.494 ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.693      ;
; 0.494 ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.693      ;
; 0.495 ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.694      ;
; 0.495 ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.694      ;
; 0.497 ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.696      ;
; 0.497 ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.696      ;
; 0.497 ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.696      ;
; 0.499 ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.698      ;
; 0.499 ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.698      ;
; 0.499 ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.698      ;
; 0.499 ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.698      ;
; 0.507 ; spi_ee_config:u_spi_ee_config|read_back                                    ; spi_ee_config:u_spi_ee_config|read_back_d                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.705      ;
; 0.511 ; spi_ee_config:u_spi_ee_config|read_ready                                   ; spi_ee_config:u_spi_ee_config|p2s_data[9]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.709      ;
; 0.512 ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.711      ;
; 0.514 ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.713      ;
; 0.517 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.716      ;
; 0.534 ; spi_ee_config:u_spi_ee_config|read_back                                    ; spi_ee_config:u_spi_ee_config|high_byte                                    ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.732      ;
; 0.535 ; spi_ee_config:u_spi_ee_config|spi_go                                       ; spi_ee_config:u_spi_ee_config|read_back                                    ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.733      ;
; 0.540 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.739      ;
; 0.541 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.740      ;
; 0.550 ; spi_ee_config:u_spi_ee_config|read_back                                    ; spi_ee_config:u_spi_ee_config|clear_status                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.748      ;
; 0.623 ; spi_ee_config:u_spi_ee_config|read_ready                                   ; spi_ee_config:u_spi_ee_config|spi_go                                       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.821      ;
; 0.672 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.871      ;
; 0.728 ; spi_ee_config:u_spi_ee_config|high_byte                                    ; spi_ee_config:u_spi_ee_config|spi_go                                       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.926      ;
; 0.737 ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.936      ;
; 0.737 ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.936      ;
; 0.738 ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.937      ;
; 0.738 ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.937      ;
; 0.738 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.937      ;
; 0.740 ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.939      ;
; 0.742 ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.941      ;
; 0.742 ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.941      ;
; 0.744 ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.943      ;
; 0.745 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[3] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.944      ;
; 0.745 ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.944      ;
; 0.746 ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.945      ;
; 0.748 ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.947      ;
; 0.748 ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.947      ;
; 0.748 ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.947      ;
; 0.748 ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.947      ;
; 0.751 ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.950      ;
; 0.752 ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.951      ;
; 0.753 ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.952      ;
; 0.755 ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.954      ;
; 0.755 ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.954      ;
; 0.755 ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.954      ;
; 0.755 ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.954      ;
; 0.768 ; spi_ee_config:u_spi_ee_config|low_byte_data[7]                             ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 0.989      ;
; 0.783 ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.982      ;
; 0.785 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.057      ; 0.986      ;
; 0.786 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[1]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.057      ; 0.987      ;
; 0.786 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[6]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.057      ; 0.987      ;
; 0.787 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.057      ; 0.988      ;
; 0.788 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.057      ; 0.989      ;
; 0.788 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[2]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.057      ; 0.989      ;
; 0.790 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[0] ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.011      ;
; 0.793 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.057      ; 0.994      ;
; 0.794 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[1] ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.015      ;
; 0.795 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.057      ; 0.996      ;
; 0.795 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.057      ; 0.996      ;
; 0.795 ; spi_ee_config:u_spi_ee_config|low_byte_data[6]                             ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.016      ;
; 0.802 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.057      ; 1.003      ;
; 0.803 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.057      ; 1.004      ;
; 0.803 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[3]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.057      ; 1.004      ;
+-------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                               ;
+--------+--------------------------------+----------------------------------------------------------------------------+--------------+------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                      ; To Node                                                                    ; Launch Clock ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------+----------------------------------------------------------------------------+--------------+------------------------------------------------------+--------------+------------+------------+
; 15.632 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.057     ; 2.256      ;
; 15.632 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.057     ; 2.256      ;
; 15.632 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[3] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.057     ; 2.256      ;
; 15.632 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.057     ; 2.256      ;
; 15.632 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.057     ; 2.256      ;
; 15.632 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.057     ; 2.256      ;
; 15.632 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.057     ; 2.256      ;
; 15.632 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.057     ; 2.256      ;
; 15.632 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.057     ; 2.256      ;
; 15.900 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[1]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.057     ; 1.988      ;
; 15.900 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[2]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.057     ; 1.988      ;
; 16.400 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.491      ;
; 16.400 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.491      ;
; 16.400 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.491      ;
; 16.400 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.491      ;
; 16.400 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.491      ;
; 16.400 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.491      ;
; 16.400 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.491      ;
; 16.400 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.491      ;
; 16.400 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.491      ;
; 16.400 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.491      ;
; 16.400 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.491      ;
; 16.400 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.491      ;
; 16.400 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.491      ;
; 16.400 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.491      ;
; 16.400 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.491      ;
; 16.420 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_back                                    ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.471      ;
; 16.420 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|high_byte                                    ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.471      ;
; 16.420 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.471      ;
; 16.420 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[0]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.471      ;
; 16.420 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[3]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.471      ;
; 16.420 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_go                                       ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.471      ;
; 16.420 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_back_d                                  ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.471      ;
; 16.420 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|high_byte_d                                  ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -2.054     ; 1.471      ;
+--------+--------------------------------+----------------------------------------------------------------------------+--------------+------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'CLOCK_50'                                                                                                              ;
+--------+--------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                      ; To Node                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; 17.585 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[19] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 2.351      ;
; 17.585 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[21] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 2.351      ;
; 17.585 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 2.351      ;
; 17.585 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 2.351      ;
; 17.818 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 2.120      ;
; 18.233 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 1.701      ;
; 18.233 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 1.701      ;
; 18.233 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 1.701      ;
; 18.233 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 1.701      ;
; 18.253 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 1.682      ;
; 18.253 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 1.682      ;
; 18.253 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 1.682      ;
; 18.253 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 1.682      ;
; 18.253 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 1.682      ;
; 18.253 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 1.682      ;
; 18.253 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 1.682      ;
; 18.253 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 1.682      ;
; 18.253 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 1.682      ;
; 18.253 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 1.682      ;
; 18.253 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 1.682      ;
; 18.253 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 1.682      ;
; 18.253 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 1.682      ;
; 18.253 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 1.682      ;
; 18.253 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 1.682      ;
+--------+--------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'CLOCK_50'                                                                                                              ;
+-------+--------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                      ; To Node                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; 1.386 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[2]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 1.580      ;
; 1.386 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[3]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 1.580      ;
; 1.386 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[5]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 1.580      ;
; 1.386 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[8]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 1.580      ;
; 1.386 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[9]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 1.580      ;
; 1.386 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[10] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 1.580      ;
; 1.386 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[11] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 1.580      ;
; 1.386 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 1.580      ;
; 1.386 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[13] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 1.580      ;
; 1.386 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 1.580      ;
; 1.386 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 1.580      ;
; 1.386 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 1.580      ;
; 1.386 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 1.580      ;
; 1.386 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 1.580      ;
; 1.386 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[0]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 1.580      ;
; 1.401 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[1]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.048      ; 1.593      ;
; 1.401 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[4]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.048      ; 1.593      ;
; 1.401 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[6]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.048      ; 1.593      ;
; 1.401 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[7]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.048      ; 1.593      ;
; 1.782 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 1.979      ;
; 2.002 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[19] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.051      ; 2.197      ;
; 2.002 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[21] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.051      ; 2.197      ;
; 2.002 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.051      ; 2.197      ;
; 2.002 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.051      ; 2.197      ;
+-------+--------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                               ;
+-------+--------------------------------+----------------------------------------------------------------------------+--------------+------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                      ; To Node                                                                    ; Launch Clock ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------+----------------------------------------------------------------------------+--------------+------------------------------------------------------+--------------+------------+------------+
; 2.758 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_back                                    ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.624     ; 1.378      ;
; 2.758 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|high_byte                                    ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.624     ; 1.378      ;
; 2.758 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.624     ; 1.378      ;
; 2.758 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[0]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.624     ; 1.378      ;
; 2.758 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[3]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.624     ; 1.378      ;
; 2.758 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_go                                       ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.624     ; 1.378      ;
; 2.758 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_back_d                                  ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.624     ; 1.378      ;
; 2.758 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|high_byte_d                                  ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.624     ; 1.378      ;
; 2.766 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.623     ; 1.387      ;
; 2.766 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.623     ; 1.387      ;
; 2.766 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.623     ; 1.387      ;
; 2.766 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.623     ; 1.387      ;
; 2.766 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.623     ; 1.387      ;
; 2.766 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.623     ; 1.387      ;
; 2.766 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.623     ; 1.387      ;
; 2.766 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.623     ; 1.387      ;
; 2.766 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.623     ; 1.387      ;
; 2.766 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.623     ; 1.387      ;
; 2.766 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.623     ; 1.387      ;
; 2.766 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.623     ; 1.387      ;
; 2.766 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.623     ; 1.387      ;
; 2.766 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.623     ; 1.387      ;
; 2.766 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.623     ; 1.387      ;
; 3.257 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[1]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.627     ; 1.874      ;
; 3.257 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[2]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.627     ; 1.874      ;
; 3.509 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.626     ; 2.127      ;
; 3.509 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.626     ; 2.127      ;
; 3.509 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[3] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.626     ; 2.127      ;
; 3.509 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.626     ; 2.127      ;
; 3.509 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.626     ; 2.127      ;
; 3.509 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.626     ; 2.127      ;
; 3.509 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.626     ; 2.127      ;
; 3.509 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.626     ; 2.127      ;
; 3.509 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.626     ; 2.127      ;
+-------+--------------------------------+----------------------------------------------------------------------------+--------------+------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                                                                                             ;
+-------+--------------+----------------+-----------------+----------+------------+----------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                         ;
+-------+--------------+----------------+-----------------+----------+------------+----------------------------------------------------------------+
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[0]                          ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[10]                         ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[11]                         ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[12]                         ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[13]                         ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[14]                         ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[16]                         ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[17]                         ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[18]                         ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[1]                          ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[20]                         ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[2]                          ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[3]                          ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[4]                          ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[5]                          ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[6]                          ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[7]                          ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[8]                          ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[9]                          ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_d[0]                              ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[0]                              ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[10]                             ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[1]                              ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[2]                              ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[3]                              ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[4]                              ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[5]                              ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[6]                              ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[7]                              ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[8]                              ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[9]                              ;
; 9.596 ; 9.780        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|oRST                                 ;
; 9.597 ; 9.781        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[15]                         ;
; 9.597 ; 9.781        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[19]                         ;
; 9.597 ; 9.781        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[21]                         ;
; 9.597 ; 9.781        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[22]                         ;
; 9.597 ; 9.781        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[23]                         ;
; 9.597 ; 9.781        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_d[1]                              ;
; 9.597 ; 9.781        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[11]                             ;
; 9.597 ; 9.781        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[12]                             ;
; 9.597 ; 9.781        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[13]                             ;
; 9.597 ; 9.781        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[14]                             ;
; 9.597 ; 9.781        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[15]                             ;
; 9.597 ; 9.781        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[16]                             ;
; 9.597 ; 9.781        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[17]                             ;
; 9.597 ; 9.781        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[18]                             ;
; 9.597 ; 9.781        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[19]                             ;
; 9.597 ; 9.781        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[20]                             ;
; 9.709 ; 9.709        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0]           ;
; 9.709 ; 9.709        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[1]           ;
; 9.709 ; 9.709        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|observablevcoout ;
; 9.751 ; 9.751        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; CLOCK_50~input|o                                               ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[0]|clk                                 ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[10]|clk                                ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[11]|clk                                ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[12]|clk                                ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[13]|clk                                ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[14]|clk                                ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[16]|clk                                ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[17]|clk                                ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[18]|clk                                ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[1]|clk                                 ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[20]|clk                                ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[2]|clk                                 ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[3]|clk                                 ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[4]|clk                                 ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[5]|clk                                 ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[6]|clk                                 ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[7]|clk                                 ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[8]|clk                                 ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[9]|clk                                 ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_d[0]|clk                                     ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[0]|clk                                      ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[10]|clk                                     ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[1]|clk                                      ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[2]|clk                                      ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[3]|clk                                      ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[4]|clk                                      ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[5]|clk                                      ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[6]|clk                                      ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[7]|clk                                      ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[8]|clk                                      ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[9]|clk                                      ;
; 9.756 ; 9.756        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|oRST|clk                                         ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[15]|clk                                ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[19]|clk                                ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[21]|clk                                ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[22]|clk                                ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[23]|clk                                ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_d[1]|clk                                     ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[11]|clk                                     ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[12]|clk                                     ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[13]|clk                                     ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[14]|clk                                     ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[15]|clk                                     ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[16]|clk                                     ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[17]|clk                                     ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[18]|clk                                     ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[19]|clk                                     ;
; 9.757 ; 9.757        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[20]|clk                                     ;
+-------+--------------+----------------+-----------------+----------+------------+----------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                            ;
+---------+--------------+----------------+------------------+------------------------------------------------------+------------+----------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock                                                ; Clock Edge ; Target                                                                     ;
+---------+--------------+----------------+------------------+------------------------------------------------------+------------+----------------------------------------------------------------------------+
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status_d[1]                            ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status_d[2]                            ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_L[5]                                   ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[3] ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status                                 ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status_d[0]                            ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status_d[3]                            ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|high_byte                                    ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|high_byte_d                                  ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|low_byte_data[5]                             ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|low_byte_data[6]                             ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|low_byte_data[7]                             ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[1]                                  ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[2]                                  ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[3]                                  ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[6]                                  ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[8]                                  ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[9]                                  ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_back                                    ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_back_d                                  ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_ready                                   ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[0] ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[1] ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[2] ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[3] ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[4] ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[5] ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[6] ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[7] ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_go                                       ;
; 249.853 ; 250.037      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ;
; 249.853 ; 250.037      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ;
; 249.853 ; 250.037      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ;
; 249.853 ; 250.037      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ;
; 249.853 ; 250.037      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ;
; 249.853 ; 250.037      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ;
; 249.853 ; 250.037      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ;
; 249.853 ; 250.037      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ;
; 249.853 ; 250.037      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ;
; 249.853 ; 250.037      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ;
; 249.853 ; 250.037      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ;
; 249.853 ; 250.037      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ;
; 249.853 ; 250.037      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ;
; 249.853 ; 250.037      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ;
; 249.853 ; 250.037      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ;
; 249.854 ; 250.038      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status                                 ;
; 249.854 ; 250.038      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status_d[0]                            ;
; 249.854 ; 250.038      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status_d[3]                            ;
; 249.854 ; 250.038      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|high_byte                                    ;
; 249.854 ; 250.038      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|high_byte_d                                  ;
; 249.854 ; 250.038      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ;
; 249.854 ; 250.038      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ;
; 249.854 ; 250.038      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ;
; 249.854 ; 250.038      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ;
; 249.854 ; 250.038      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|low_byte_data[5]                             ;
; 249.854 ; 250.038      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|low_byte_data[6]                             ;
; 249.854 ; 250.038      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|low_byte_data[7]                             ;
; 249.854 ; 250.038      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ;
; 249.854 ; 250.038      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ;
; 249.854 ; 250.038      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_L[5]                                   ;
; 249.854 ; 250.038      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ;
; 249.854 ; 250.038      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ;
; 249.854 ; 250.038      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ;
; 249.854 ; 250.038      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ;
; 249.854 ; 250.038      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ;
+---------+--------------+----------------+------------------+------------------------------------------------------+------------+----------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                         ;
+--------------+------------+----------+----------+------------+------------------------------------------------------+
; Data Port    ; Clock Port ; Rise     ; Fall     ; Clock Edge ; Clock Reference                                      ;
+--------------+------------+----------+----------+------------+------------------------------------------------------+
; G_SENSOR_INT ; CLOCK_50   ; 0.335    ; 0.560    ; Rise       ; CLOCK_50                                             ;
; G_SENSOR_INT ; CLOCK_50   ; -195.988 ; -195.881 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SDAT     ; CLOCK_50   ; -196.615 ; -196.183 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
+--------------+------------+----------+----------+------------+------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                        ;
+--------------+------------+---------+---------+------------+------------------------------------------------------+
; Data Port    ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                      ;
+--------------+------------+---------+---------+------------+------------------------------------------------------+
; G_SENSOR_INT ; CLOCK_50   ; -0.062  ; -0.287  ; Rise       ; CLOCK_50                                             ;
; G_SENSOR_INT ; CLOCK_50   ; 197.319 ; 197.218 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SDAT     ; CLOCK_50   ; 197.227 ; 196.810 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
+--------------+------------+---------+---------+------------+------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                              ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+
; Data Port     ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                      ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+
; LED[*]        ; CLOCK_50   ; 10.289  ; 10.680  ; Rise       ; CLOCK_50                                             ;
;  LED[0]       ; CLOCK_50   ; 7.653   ; 7.536   ; Rise       ; CLOCK_50                                             ;
;  LED[1]       ; CLOCK_50   ; 8.088   ; 7.961   ; Rise       ; CLOCK_50                                             ;
;  LED[2]       ; CLOCK_50   ; 7.337   ; 7.262   ; Rise       ; CLOCK_50                                             ;
;  LED[3]       ; CLOCK_50   ; 8.256   ; 8.102   ; Rise       ; CLOCK_50                                             ;
;  LED[4]       ; CLOCK_50   ; 8.612   ; 8.393   ; Rise       ; CLOCK_50                                             ;
;  LED[5]       ; CLOCK_50   ; 8.193   ; 8.623   ; Rise       ; CLOCK_50                                             ;
;  LED[6]       ; CLOCK_50   ; 7.955   ; 7.971   ; Rise       ; CLOCK_50                                             ;
;  LED[7]       ; CLOCK_50   ; 10.289  ; 10.680  ; Rise       ; CLOCK_50                                             ;
; G_SENSOR_CS_N ; CLOCK_50   ; 203.740 ; 203.779 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SCLK      ; CLOCK_50   ; 204.716 ; 204.489 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SDAT      ; CLOCK_50   ; 206.867 ; 206.743 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; LED[*]        ; CLOCK_50   ; 209.306 ; 209.833 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[0]       ; CLOCK_50   ; 206.209 ; 206.108 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[1]       ; CLOCK_50   ; 206.846 ; 206.686 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[2]       ; CLOCK_50   ; 206.551 ; 206.456 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[3]       ; CLOCK_50   ; 207.042 ; 206.821 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[4]       ; CLOCK_50   ; 207.398 ; 207.112 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[5]       ; CLOCK_50   ; 207.878 ; 208.296 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[6]       ; CLOCK_50   ; 206.972 ; 207.124 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[7]       ; CLOCK_50   ; 209.306 ; 209.833 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SCLK      ; CLOCK_50   ; 170.384 ;         ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[1] ;
; I2C_SCLK      ; CLOCK_50   ;         ; 170.163 ; Fall       ; u_spipll|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                      ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+
; Data Port     ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                      ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+
; LED[*]        ; CLOCK_50   ; 6.801   ; 6.693   ; Rise       ; CLOCK_50                                             ;
;  LED[0]       ; CLOCK_50   ; 7.128   ; 7.015   ; Rise       ; CLOCK_50                                             ;
;  LED[1]       ; CLOCK_50   ; 7.112   ; 6.970   ; Rise       ; CLOCK_50                                             ;
;  LED[2]       ; CLOCK_50   ; 6.811   ; 6.693   ; Rise       ; CLOCK_50                                             ;
;  LED[3]       ; CLOCK_50   ; 7.193   ; 7.060   ; Rise       ; CLOCK_50                                             ;
;  LED[4]       ; CLOCK_50   ; 7.532   ; 7.334   ; Rise       ; CLOCK_50                                             ;
;  LED[5]       ; CLOCK_50   ; 7.810   ; 8.191   ; Rise       ; CLOCK_50                                             ;
;  LED[6]       ; CLOCK_50   ; 6.801   ; 6.872   ; Rise       ; CLOCK_50                                             ;
;  LED[7]       ; CLOCK_50   ; 9.425   ; 9.829   ; Rise       ; CLOCK_50                                             ;
; G_SENSOR_CS_N ; CLOCK_50   ; 203.260 ; 203.300 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SCLK      ; CLOCK_50   ; 204.170 ; 203.956 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SDAT      ; CLOCK_50   ; 203.872 ; 203.680 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; LED[*]        ; CLOCK_50   ; 204.002 ; 203.910 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[0]       ; CLOCK_50   ; 204.832 ; 204.715 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[1]       ; CLOCK_50   ; 205.248 ; 205.176 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[2]       ; CLOCK_50   ; 204.002 ; 203.910 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[3]       ; CLOCK_50   ; 204.655 ; 204.573 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[4]       ; CLOCK_50   ; 204.864 ; 204.643 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[5]       ; CLOCK_50   ; 205.467 ; 205.782 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[6]       ; CLOCK_50   ; 204.479 ; 204.502 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[7]       ; CLOCK_50   ; 207.213 ; 207.595 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SCLK      ; CLOCK_50   ; 169.919 ;         ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[1] ;
; I2C_SCLK      ; CLOCK_50   ;         ; 169.704 ; Fall       ; u_spipll|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+


+--------------------------------------------------------------+
; Propagation Delay                                            ;
+--------------+-------------+-------+--------+--------+-------+
; Input Port   ; Output Port ; RR    ; RF     ; FR     ; FF    ;
+--------------+-------------+-------+--------+--------+-------+
; G_SENSOR_INT ; LED[0]      ; 6.804 ; 7.309  ; 7.593  ; 6.885 ;
; G_SENSOR_INT ; LED[1]      ; 8.258 ; 7.908  ; 8.209  ; 8.331 ;
; G_SENSOR_INT ; LED[2]      ; 7.895 ; 7.800  ; 8.021  ; 7.955 ;
; G_SENSOR_INT ; LED[3]      ; 8.386 ; 7.921  ; 8.177  ; 8.426 ;
; G_SENSOR_INT ; LED[4]      ; 8.742 ; 8.214  ; 8.534  ; 8.717 ;
; G_SENSOR_INT ; LED[5]      ; 9.222 ; 9.640  ; 9.348  ; 9.795 ;
; G_SENSOR_INT ; LED[6]      ; 7.351 ; 8.468  ; 8.577  ; 7.536 ;
; G_SENSOR_INT ; LED[7]      ; 9.205 ; 11.177 ; 10.911 ; 9.808 ;
+--------------+-------------+-------+--------+--------+-------+


+------------------------------------------------------------+
; Minimum Propagation Delay                                  ;
+--------------+-------------+-------+-------+-------+-------+
; Input Port   ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+--------------+-------------+-------+-------+-------+-------+
; G_SENSOR_INT ; LED[0]      ; 6.564 ; 6.872 ; 7.219 ; 6.649 ;
; G_SENSOR_INT ; LED[1]      ; 7.571 ; 7.018 ; 7.348 ; 7.673 ;
; G_SENSOR_INT ; LED[2]      ; 6.684 ; 6.479 ; 6.795 ; 6.820 ;
; G_SENSOR_INT ; LED[3]      ; 6.721 ; 6.614 ; 6.943 ; 6.830 ;
; G_SENSOR_INT ; LED[4]      ; 7.064 ; 6.897 ; 7.286 ; 7.113 ;
; G_SENSOR_INT ; LED[5]      ; 7.989 ; 8.309 ; 8.100 ; 8.650 ;
; G_SENSOR_INT ; LED[6]      ; 6.754 ; 6.322 ; 6.520 ; 7.020 ;
; G_SENSOR_INT ; LED[7]      ; 8.920 ; 9.752 ; 9.575 ; 9.529 ;
+--------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                            ;
+-----------+------------+---------+---------+------------+------------------------------------------------------+
; Data Port ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                      ;
+-----------+------------+---------+---------+------------+------------------------------------------------------+
; I2C_SDAT  ; CLOCK_50   ; 204.805 ; 204.663 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+---------+---------+------------+------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                    ;
+-----------+------------+---------+---------+------------+------------------------------------------------------+
; Data Port ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                      ;
+-----------+------------+---------+---------+------------+------------------------------------------------------+
; I2C_SDAT  ; CLOCK_50   ; 203.822 ; 203.680 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+---------+---------+------------+------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                               ;
+-----------+------------+-----------+-----------+------------+------------------------------------------------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                      ;
+-----------+------------+-----------+-----------+------------+------------------------------------------------------+
; I2C_SDAT  ; CLOCK_50   ; 204.541   ; 204.683   ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-----------+-----------+------------+------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                       ;
+-----------+------------+-----------+-----------+------------+------------------------------------------------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                      ;
+-----------+------------+-----------+-----------+------------+------------------------------------------------------+
; I2C_SDAT  ; CLOCK_50   ; 203.632   ; 203.774   ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-----------+-----------+------------+------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                            ;
+------------------------------------------------------+--------+---------------+
; Clock                                                ; Slack  ; End Point TNS ;
+------------------------------------------------------+--------+---------------+
; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 17.117 ; 0.000         ;
; CLOCK_50                                             ; 17.793 ; 0.000         ;
+------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                            ;
+------------------------------------------------------+-------+---------------+
; Clock                                                ; Slack ; End Point TNS ;
+------------------------------------------------------+-------+---------------+
; CLOCK_50                                             ; 0.187 ; 0.000         ;
; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.188 ; 0.000         ;
+------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                         ;
+------------------------------------------------------+--------+---------------+
; Clock                                                ; Slack  ; End Point TNS ;
+------------------------------------------------------+--------+---------------+
; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 17.033 ; 0.000         ;
; CLOCK_50                                             ; 18.410 ; 0.000         ;
+------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                         ;
+------------------------------------------------------+-------+---------------+
; Clock                                                ; Slack ; End Point TNS ;
+------------------------------------------------------+-------+---------------+
; CLOCK_50                                             ; 0.830 ; 0.000         ;
; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 1.739 ; 0.000         ;
+------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                               ;
+------------------------------------------------------+---------+---------------+
; Clock                                                ; Slack   ; End Point TNS ;
+------------------------------------------------------+---------+---------------+
; CLOCK_50                                             ; 9.273   ; 0.000         ;
; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 249.781 ; 0.000         ;
+------------------------------------------------------+---------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                       ;
+---------+--------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                  ; To Node                                                                    ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+---------+--------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 17.117  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.424      ;
; 17.117  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.424      ;
; 17.117  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.424      ;
; 17.117  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.424      ;
; 17.117  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.424      ;
; 17.129  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.390     ; 1.418      ;
; 17.129  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.390     ; 1.418      ;
; 17.129  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.390     ; 1.418      ;
; 17.129  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.390     ; 1.418      ;
; 17.129  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|oDATA_L[5]                                   ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.390     ; 1.418      ;
; 17.231  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|low_byte_data[6]                             ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.310      ;
; 17.231  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|low_byte_data[7]                             ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.310      ;
; 17.231  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|low_byte_data[5]                             ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.310      ;
; 17.243  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[8]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.298      ;
; 17.243  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[9]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.298      ;
; 17.405  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.136      ;
; 17.405  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.136      ;
; 17.405  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.136      ;
; 17.405  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[1]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.136      ;
; 17.405  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[3]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.136      ;
; 17.405  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[2]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.136      ;
; 17.405  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|p2s_data[6]                                  ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.136      ;
; 17.503  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[0] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.038      ;
; 17.503  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[1] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.038      ;
; 17.503  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[2] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.038      ;
; 17.503  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[3] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.038      ;
; 17.503  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[4] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.038      ;
; 17.503  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[5] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.038      ;
; 17.503  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[6] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.038      ;
; 17.503  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[7] ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 1.038      ;
; 17.779  ; reset_delay:u_reset_delay|oRST             ; spi_ee_config:u_spi_ee_config|read_ready                                   ; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.762      ;
; 497.907 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.037     ; 2.043      ;
; 497.907 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.037     ; 2.043      ;
; 497.907 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.037     ; 2.043      ;
; 497.907 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.037     ; 2.043      ;
; 497.907 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|oDATA_L[5]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.037     ; 2.043      ;
; 497.907 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.037     ; 2.043      ;
; 497.907 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.037     ; 2.043      ;
; 497.907 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.037     ; 2.043      ;
; 497.907 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.037     ; 2.043      ;
; 497.907 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|oDATA_L[5]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.037     ; 2.043      ;
; 497.908 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.047      ;
; 497.908 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.047      ;
; 497.908 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.047      ;
; 497.908 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.047      ;
; 497.908 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.047      ;
; 497.908 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.047      ;
; 497.908 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.047      ;
; 497.908 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.047      ;
; 497.908 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.047      ;
; 497.908 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.047      ;
; 497.909 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.046      ;
; 497.909 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.046      ;
; 497.909 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.046      ;
; 497.909 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[1]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.046      ;
; 497.909 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[3]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.046      ;
; 497.909 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[2]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.046      ;
; 497.909 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[6]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.046      ;
; 497.909 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.046      ;
; 497.909 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.046      ;
; 497.909 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.046      ;
; 497.909 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[1]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.046      ;
; 497.909 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[3]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.046      ;
; 497.909 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[2]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.046      ;
; 497.909 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[6]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.046      ;
; 497.949 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.037     ; 2.001      ;
; 497.949 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.037     ; 2.001      ;
; 497.949 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.037     ; 2.001      ;
; 497.949 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.037     ; 2.001      ;
; 497.949 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|oDATA_L[5]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.037     ; 2.001      ;
; 497.950 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.005      ;
; 497.950 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.005      ;
; 497.950 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.005      ;
; 497.950 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.005      ;
; 497.950 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.005      ;
; 497.951 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.004      ;
; 497.951 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.004      ;
; 497.951 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.004      ;
; 497.951 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[1]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.004      ;
; 497.951 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[3]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.004      ;
; 497.951 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[2]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.004      ;
; 497.951 ; spi_ee_config:u_spi_ee_config|ini_index[1] ; spi_ee_config:u_spi_ee_config|p2s_data[6]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 2.004      ;
; 498.020 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|low_byte_data[6]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 1.935      ;
; 498.020 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|low_byte_data[7]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 1.935      ;
; 498.020 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|low_byte_data[5]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 1.935      ;
; 498.020 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|low_byte_data[6]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 1.935      ;
; 498.020 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|low_byte_data[7]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 1.935      ;
; 498.020 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|low_byte_data[5]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 1.935      ;
; 498.031 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[8]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 1.924      ;
; 498.031 ; spi_ee_config:u_spi_ee_config|ini_index[2] ; spi_ee_config:u_spi_ee_config|p2s_data[9]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 1.924      ;
; 498.031 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[8]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 1.924      ;
; 498.031 ; spi_ee_config:u_spi_ee_config|ini_index[0] ; spi_ee_config:u_spi_ee_config|p2s_data[9]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 1.924      ;
; 498.048 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.037     ; 1.902      ;
; 498.048 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.037     ; 1.902      ;
; 498.048 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.037     ; 1.902      ;
; 498.048 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.037     ; 1.902      ;
; 498.048 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|oDATA_L[5]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.037     ; 1.902      ;
; 498.049 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 1.906      ;
; 498.049 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 1.906      ;
; 498.049 ; spi_ee_config:u_spi_ee_config|ini_index[3] ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 500.000      ; -0.032     ; 1.906      ;
+---------+--------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'CLOCK_50'                                                                                                                         ;
+--------+----------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                              ; To Node                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; 17.793 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.158      ;
; 17.820 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.131      ;
; 17.830 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.122      ;
; 17.836 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.115      ;
; 17.853 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.098      ;
; 17.885 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.066      ;
; 17.980 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.972      ;
; 18.008 ; led_driver:u_led_driver|int2_count[4]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.944      ;
; 18.009 ; led_driver:u_led_driver|int2_count[9]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.942      ;
; 18.010 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.941      ;
; 18.013 ; led_driver:u_led_driver|int2_count[12] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.938      ;
; 18.027 ; led_driver:u_led_driver|int2_count[7]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.925      ;
; 18.032 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.920      ;
; 18.035 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.917      ;
; 18.042 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 1.911      ;
; 18.048 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.904      ;
; 18.052 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.899      ;
; 18.052 ; led_driver:u_led_driver|int2_count[8]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.899      ;
; 18.062 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.889      ;
; 18.065 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.886      ;
; 18.072 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.880      ;
; 18.075 ; led_driver:u_led_driver|int2_count[6]  ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.877      ;
; 18.078 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.873      ;
; 18.079 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.872      ;
; 18.089 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.863      ;
; 18.090 ; led_driver:u_led_driver|int2_count[11] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.861      ;
; 18.095 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.856      ;
; 18.097 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.855      ;
; 18.111 ; led_driver:u_led_driver|int2_count[14] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.840      ;
; 18.112 ; led_driver:u_led_driver|int2_count[17] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.839      ;
; 18.112 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.839      ;
; 18.121 ; led_driver:u_led_driver|int2_count[10] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.830      ;
; 18.127 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.824      ;
; 18.144 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.807      ;
; 18.146 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.805      ;
; 18.173 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.778      ;
; 18.177 ; led_driver:u_led_driver|int2_count[16] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.774      ;
; 18.183 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.769      ;
; 18.187 ; led_driver:u_led_driver|int2_count[4]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 1.766      ;
; 18.189 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.762      ;
; 18.200 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.751      ;
; 18.202 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.749      ;
; 18.206 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.745      ;
; 18.211 ; led_driver:u_led_driver|int2_count[15] ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 1.738      ;
; 18.217 ; led_driver:u_led_driver|int2_count[4]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.735      ;
; 18.221 ; led_driver:u_led_driver|int2_count[12] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.731      ;
; 18.221 ; led_driver:u_led_driver|int2_count[9]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.731      ;
; 18.227 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.724      ;
; 18.229 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.722      ;
; 18.236 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 1.717      ;
; 18.236 ; led_driver:u_led_driver|int2_count[8]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.716      ;
; 18.237 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.715      ;
; 18.238 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.713      ;
; 18.239 ; led_driver:u_led_driver|int2_count[7]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 1.714      ;
; 18.239 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.713      ;
; 18.243 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.708      ;
; 18.247 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.705      ;
; 18.251 ; led_driver:u_led_driver|int2_count[12] ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.700      ;
; 18.251 ; led_driver:u_led_driver|int2_count[9]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.700      ;
; 18.254 ; led_driver:u_led_driver|int2_count[6]  ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 1.699      ;
; 18.260 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.691      ;
; 18.262 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.689      ;
; 18.266 ; led_driver:u_led_driver|int2_count[8]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.685      ;
; 18.267 ; led_driver:u_led_driver|int2_count[4]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.685      ;
; 18.268 ; led_driver:u_led_driver|int2_count[9]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.683      ;
; 18.269 ; led_driver:u_led_driver|int2_count[7]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.683      ;
; 18.272 ; led_driver:u_led_driver|int2_count[12] ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.679      ;
; 18.274 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.678      ;
; 18.278 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[19] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.674      ;
; 18.284 ; led_driver:u_led_driver|int2_count[6]  ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.668      ;
; 18.284 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 1.669      ;
; 18.285 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[21] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.667      ;
; 18.286 ; led_driver:u_led_driver|int2_count[7]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.666      ;
; 18.288 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 1.665      ;
; 18.290 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.662      ;
; 18.291 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 1.662      ;
; 18.292 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.659      ;
; 18.294 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.657      ;
; 18.298 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 1.656      ;
; 18.302 ; led_driver:u_led_driver|int2_count[11] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.650      ;
; 18.304 ; led_driver:u_led_driver|int2_count[10] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.648      ;
; 18.304 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 1.649      ;
; 18.307 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.645      ;
; 18.310 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.641      ;
; 18.311 ; led_driver:u_led_driver|int2_count[8]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.640      ;
; 18.316 ; led_driver:u_led_driver|int2_count[14] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.636      ;
; 18.319 ; led_driver:u_led_driver|int2_count[0]  ; led_driver:u_led_driver|int2_count[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.632      ;
; 18.324 ; led_driver:u_led_driver|int2_count[17] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.628      ;
; 18.330 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[19] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.622      ;
; 18.332 ; led_driver:u_led_driver|int2_count[11] ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.619      ;
; 18.333 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[19] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.619      ;
; 18.334 ; led_driver:u_led_driver|int2_count[10] ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.617      ;
; 18.334 ; led_driver:u_led_driver|int2_count[6]  ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.618      ;
; 18.337 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[21] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.615      ;
; 18.339 ; led_driver:u_led_driver|int2_count[5]  ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.613      ;
; 18.340 ; led_driver:u_led_driver|int2_count[2]  ; led_driver:u_led_driver|int2_count[21] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.612      ;
; 18.340 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[19] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 1.613      ;
; 18.346 ; led_driver:u_led_driver|int2_count[14] ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.605      ;
; 18.346 ; led_driver:u_led_driver|int2_count[13] ; led_driver:u_led_driver|int2_count[19] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 1.606      ;
; 18.346 ; led_driver:u_led_driver|int2_count[3]  ; led_driver:u_led_driver|int2_count[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 1.605      ;
+--------+----------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'CLOCK_50'                                                                                                                         ;
+-------+----------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                              ; To Node                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.187 ; reset_delay:u_reset_delay|cont[20]     ; reset_delay:u_reset_delay|cont[20]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; led_driver:u_led_driver|int2_count[23] ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.194 ; reset_delay:u_reset_delay|cont[0]      ; reset_delay:u_reset_delay|cont[0]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.314      ;
; 0.292 ; reset_delay:u_reset_delay|cont[10]     ; reset_delay:u_reset_delay|cont[10]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.412      ;
; 0.293 ; reset_delay:u_reset_delay|cont[6]      ; reset_delay:u_reset_delay|cont[6]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.413      ;
; 0.293 ; reset_delay:u_reset_delay|cont[8]      ; reset_delay:u_reset_delay|cont[8]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.413      ;
; 0.293 ; reset_delay:u_reset_delay|cont[14]     ; reset_delay:u_reset_delay|cont[14]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.413      ;
; 0.294 ; reset_delay:u_reset_delay|cont[2]      ; reset_delay:u_reset_delay|cont[2]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; reset_delay:u_reset_delay|cont[4]      ; reset_delay:u_reset_delay|cont[4]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; reset_delay:u_reset_delay|cont[11]     ; reset_delay:u_reset_delay|cont[11]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; reset_delay:u_reset_delay|cont[12]     ; reset_delay:u_reset_delay|cont[12]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; reset_delay:u_reset_delay|cont[16]     ; reset_delay:u_reset_delay|cont[16]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.414      ;
; 0.295 ; reset_delay:u_reset_delay|cont[3]      ; reset_delay:u_reset_delay|cont[3]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; reset_delay:u_reset_delay|cont[7]      ; reset_delay:u_reset_delay|cont[7]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; reset_delay:u_reset_delay|cont[9]      ; reset_delay:u_reset_delay|cont[9]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; reset_delay:u_reset_delay|cont[13]     ; reset_delay:u_reset_delay|cont[13]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; reset_delay:u_reset_delay|cont[17]     ; reset_delay:u_reset_delay|cont[17]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; reset_delay:u_reset_delay|cont[18]     ; reset_delay:u_reset_delay|cont[18]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.415      ;
; 0.296 ; reset_delay:u_reset_delay|cont[5]      ; reset_delay:u_reset_delay|cont[5]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.416      ;
; 0.296 ; reset_delay:u_reset_delay|cont[15]     ; reset_delay:u_reset_delay|cont[15]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.416      ;
; 0.296 ; reset_delay:u_reset_delay|cont[19]     ; reset_delay:u_reset_delay|cont[19]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.416      ;
; 0.300 ; reset_delay:u_reset_delay|cont[0]      ; reset_delay:u_reset_delay|cont[1]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.420      ;
; 0.317 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.437      ;
; 0.359 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[11] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.477      ;
; 0.361 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.479      ;
; 0.362 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[3]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.480      ;
; 0.368 ; reset_delay:u_reset_delay|cont[1]      ; reset_delay:u_reset_delay|cont[1]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.488      ;
; 0.369 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.488      ;
; 0.370 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[21] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.489      ;
; 0.371 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[0]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.489      ;
; 0.372 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[2]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.490      ;
; 0.387 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[10] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.507      ;
; 0.390 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.510      ;
; 0.391 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[8]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.511      ;
; 0.391 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[9]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.511      ;
; 0.393 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[5]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.513      ;
; 0.394 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.514      ;
; 0.396 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[11] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.516      ;
; 0.396 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.516      ;
; 0.398 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.518      ;
; 0.399 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.519      ;
; 0.399 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[13] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.519      ;
; 0.400 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.520      ;
; 0.410 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[7]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.529      ;
; 0.413 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_d[1]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 0.535      ;
; 0.417 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 0.539      ;
; 0.421 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[19] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.540      ;
; 0.430 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.549      ;
; 0.439 ; reset_delay:u_reset_delay|cont[10]     ; reset_delay:u_reset_delay|cont[11]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 0.561      ;
; 0.442 ; reset_delay:u_reset_delay|cont[6]      ; reset_delay:u_reset_delay|cont[7]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.562      ;
; 0.442 ; reset_delay:u_reset_delay|cont[8]      ; reset_delay:u_reset_delay|cont[9]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.562      ;
; 0.442 ; reset_delay:u_reset_delay|cont[14]     ; reset_delay:u_reset_delay|cont[15]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.562      ;
; 0.443 ; reset_delay:u_reset_delay|cont[2]      ; reset_delay:u_reset_delay|cont[3]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.563      ;
; 0.443 ; reset_delay:u_reset_delay|cont[12]     ; reset_delay:u_reset_delay|cont[13]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.563      ;
; 0.443 ; reset_delay:u_reset_delay|cont[16]     ; reset_delay:u_reset_delay|cont[17]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.563      ;
; 0.443 ; reset_delay:u_reset_delay|cont[4]      ; reset_delay:u_reset_delay|cont[5]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.563      ;
; 0.444 ; reset_delay:u_reset_delay|cont[18]     ; reset_delay:u_reset_delay|cont[19]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.564      ;
; 0.445 ; led_driver:u_led_driver|int2_count[1]  ; led_driver:u_led_driver|int2_count[1]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.565      ;
; 0.447 ; led_driver:u_led_driver|int2_count[22] ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.567      ;
; 0.447 ; led_driver:u_led_driver|int2_count[21] ; led_driver:u_led_driver|int2_count[21] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.567      ;
; 0.449 ; led_driver:u_led_driver|int2_count[4]  ; led_driver:u_led_driver|int2_count[4]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.569      ;
; 0.451 ; led_driver:u_led_driver|int2_count[6]  ; led_driver:u_led_driver|int2_count[6]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.571      ;
; 0.452 ; reset_delay:u_reset_delay|cont[0]      ; reset_delay:u_reset_delay|cont[2]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.572      ;
; 0.452 ; reset_delay:u_reset_delay|cont[11]     ; reset_delay:u_reset_delay|cont[12]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.572      ;
; 0.453 ; reset_delay:u_reset_delay|cont[9]      ; reset_delay:u_reset_delay|cont[10]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.573      ;
; 0.453 ; reset_delay:u_reset_delay|cont[7]      ; reset_delay:u_reset_delay|cont[8]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.573      ;
; 0.453 ; reset_delay:u_reset_delay|cont[13]     ; reset_delay:u_reset_delay|cont[14]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.573      ;
; 0.453 ; reset_delay:u_reset_delay|cont[3]      ; reset_delay:u_reset_delay|cont[4]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.573      ;
; 0.453 ; reset_delay:u_reset_delay|cont[17]     ; reset_delay:u_reset_delay|cont[18]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.573      ;
; 0.454 ; reset_delay:u_reset_delay|cont[5]      ; reset_delay:u_reset_delay|cont[6]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.574      ;
; 0.454 ; reset_delay:u_reset_delay|cont[15]     ; reset_delay:u_reset_delay|cont[16]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.574      ;
; 0.454 ; reset_delay:u_reset_delay|cont[9]      ; reset_delay:u_reset_delay|cont[11]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 0.576      ;
; 0.455 ; reset_delay:u_reset_delay|cont[0]      ; reset_delay:u_reset_delay|cont[3]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.575      ;
; 0.455 ; reset_delay:u_reset_delay|cont[11]     ; reset_delay:u_reset_delay|cont[13]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.575      ;
; 0.456 ; reset_delay:u_reset_delay|cont[7]      ; reset_delay:u_reset_delay|cont[9]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; reset_delay:u_reset_delay|cont[13]     ; reset_delay:u_reset_delay|cont[15]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; reset_delay:u_reset_delay|cont[3]      ; reset_delay:u_reset_delay|cont[5]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; reset_delay:u_reset_delay|cont[17]     ; reset_delay:u_reset_delay|cont[19]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.576      ;
; 0.457 ; reset_delay:u_reset_delay|cont[5]      ; reset_delay:u_reset_delay|cont[7]      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.577      ;
; 0.457 ; reset_delay:u_reset_delay|cont[15]     ; reset_delay:u_reset_delay|cont[17]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.577      ;
; 0.460 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.578      ;
; 0.461 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.579      ;
; 0.463 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[13] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.581      ;
; 0.464 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.582      ;
; 0.467 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[2]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.587      ;
; 0.467 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.585      ;
; 0.468 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[0]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.588      ;
; 0.472 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[5]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.590      ;
; 0.473 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[8]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.591      ;
; 0.474 ; led_driver:u_led_driver|int2_d[0]      ; led_driver:u_led_driver|int2_count[3]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.594      ;
; 0.474 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[9]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.592      ;
; 0.475 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.593      ;
; 0.480 ; led_driver:u_led_driver|int2_d[1]      ; led_driver:u_led_driver|int2_count[10] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.598      ;
; 0.493 ; reset_delay:u_reset_delay|cont[20]     ; reset_delay:u_reset_delay|cont[11]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.613      ;
; 0.493 ; reset_delay:u_reset_delay|cont[20]     ; reset_delay:u_reset_delay|cont[12]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.613      ;
; 0.493 ; reset_delay:u_reset_delay|cont[20]     ; reset_delay:u_reset_delay|cont[13]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.613      ;
; 0.493 ; reset_delay:u_reset_delay|cont[20]     ; reset_delay:u_reset_delay|cont[14]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.613      ;
; 0.493 ; reset_delay:u_reset_delay|cont[20]     ; reset_delay:u_reset_delay|cont[15]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.613      ;
; 0.493 ; reset_delay:u_reset_delay|cont[20]     ; reset_delay:u_reset_delay|cont[16]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.613      ;
; 0.493 ; reset_delay:u_reset_delay|cont[20]     ; reset_delay:u_reset_delay|cont[17]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.613      ;
+-------+----------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                      ;
+-------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                  ; To Node                                                                    ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 0.188 ; spi_ee_config:u_spi_ee_config|high_byte                                    ; spi_ee_config:u_spi_ee_config|high_byte                                    ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; spi_ee_config:u_spi_ee_config|clear_status                                 ; spi_ee_config:u_spi_ee_config|clear_status                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; spi_ee_config:u_spi_ee_config|read_ready                                   ; spi_ee_config:u_spi_ee_config|read_ready                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; spi_ee_config:u_spi_ee_config|spi_go                                       ; spi_ee_config:u_spi_ee_config|spi_go                                       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.194 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[4] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[5] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.313      ;
; 0.195 ; spi_ee_config:u_spi_ee_config|clear_status_d[1]                            ; spi_ee_config:u_spi_ee_config|clear_status_d[2]                            ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[2] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[3] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[3] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[4] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[7] ; spi_ee_config:u_spi_ee_config|low_byte_data[7]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
; 0.199 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[6] ; spi_ee_config:u_spi_ee_config|low_byte_data[6]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.318      ;
; 0.200 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[6] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[7] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.319      ;
; 0.205 ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.324      ;
; 0.207 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[1] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[2] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.326      ;
; 0.208 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[0] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[1] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.327      ;
; 0.220 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.339      ;
; 0.222 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.341      ;
; 0.224 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[3] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.343      ;
; 0.225 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.344      ;
; 0.268 ; spi_ee_config:u_spi_ee_config|clear_status                                 ; spi_ee_config:u_spi_ee_config|clear_status_d[0]                            ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.387      ;
; 0.270 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[5] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[6] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.389      ;
; 0.271 ; spi_ee_config:u_spi_ee_config|high_byte                                    ; spi_ee_config:u_spi_ee_config|p2s_data[8]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.390      ;
; 0.271 ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.390      ;
; 0.273 ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.392      ;
; 0.274 ; spi_ee_config:u_spi_ee_config|high_byte                                    ; spi_ee_config:u_spi_ee_config|p2s_data[9]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.393      ;
; 0.275 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[5] ; spi_ee_config:u_spi_ee_config|low_byte_data[5]                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.394      ;
; 0.284 ; spi_ee_config:u_spi_ee_config|high_byte                                    ; spi_ee_config:u_spi_ee_config|high_byte_d                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.403      ;
; 0.294 ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.413      ;
; 0.295 ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.414      ;
; 0.295 ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.414      ;
; 0.295 ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.414      ;
; 0.295 ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.414      ;
; 0.296 ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.296 ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.296 ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.296 ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.297 ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.416      ;
; 0.297 ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.416      ;
; 0.297 ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.416      ;
; 0.297 ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.416      ;
; 0.298 ; spi_ee_config:u_spi_ee_config|read_back                                    ; spi_ee_config:u_spi_ee_config|read_back_d                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.417      ;
; 0.305 ; spi_ee_config:u_spi_ee_config|read_ready                                   ; spi_ee_config:u_spi_ee_config|p2s_data[9]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.424      ;
; 0.306 ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.425      ;
; 0.307 ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.426      ;
; 0.313 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.432      ;
; 0.320 ; spi_ee_config:u_spi_ee_config|spi_go                                       ; spi_ee_config:u_spi_ee_config|read_back                                    ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.439      ;
; 0.325 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.444      ;
; 0.326 ; spi_ee_config:u_spi_ee_config|read_back                                    ; spi_ee_config:u_spi_ee_config|high_byte                                    ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.445      ;
; 0.326 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.445      ;
; 0.332 ; spi_ee_config:u_spi_ee_config|read_back                                    ; spi_ee_config:u_spi_ee_config|clear_status                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.451      ;
; 0.374 ; spi_ee_config:u_spi_ee_config|read_ready                                   ; spi_ee_config:u_spi_ee_config|spi_go                                       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.493      ;
; 0.399 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.518      ;
; 0.435 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[3] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.554      ;
; 0.436 ; spi_ee_config:u_spi_ee_config|low_byte_data[7]                             ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.052      ; 0.572      ;
; 0.440 ; spi_ee_config:u_spi_ee_config|high_byte                                    ; spi_ee_config:u_spi_ee_config|spi_go                                       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.559      ;
; 0.440 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.559      ;
; 0.443 ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.562      ;
; 0.444 ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.563      ;
; 0.444 ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.563      ;
; 0.444 ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.563      ;
; 0.444 ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.563      ;
; 0.445 ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.564      ;
; 0.445 ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.564      ;
; 0.450 ; spi_ee_config:u_spi_ee_config|low_byte_data[6]                             ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.052      ; 0.586      ;
; 0.451 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[1] ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.052      ; 0.587      ;
; 0.453 ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.572      ;
; 0.454 ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.573      ;
; 0.454 ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.573      ;
; 0.454 ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[0] ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.052      ; 0.590      ;
; 0.455 ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.574      ;
; 0.455 ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.574      ;
; 0.455 ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.574      ;
; 0.455 ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.574      ;
; 0.456 ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.575      ;
; 0.457 ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.576      ;
; 0.457 ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.576      ;
; 0.458 ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.577      ;
; 0.458 ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.577      ;
; 0.458 ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.577      ;
; 0.458 ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.577      ;
; 0.463 ; spi_ee_config:u_spi_ee_config|low_byte_data[5]                             ; spi_ee_config:u_spi_ee_config|oDATA_L[5]                                   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.052      ; 0.599      ;
; 0.467 ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.586      ;
; 0.469 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.591      ;
; 0.469 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.591      ;
; 0.471 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[6]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.593      ;
; 0.472 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[2]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.594      ;
; 0.473 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.595      ;
; 0.473 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[3]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.595      ;
; 0.473 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.595      ;
; 0.474 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.596      ;
; 0.474 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.596      ;
; 0.474 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.596      ;
; 0.474 ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; spi_ee_config:u_spi_ee_config|p2s_data[1]                                  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.596      ;
+-------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                               ;
+--------+--------------------------------+----------------------------------------------------------------------------+--------------+------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                      ; To Node                                                                    ; Launch Clock ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------+----------------------------------------------------------------------------+--------------+------------------------------------------------------+--------------+------------+------------+
; 17.033 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.399     ; 1.505      ;
; 17.033 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.399     ; 1.505      ;
; 17.033 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[3] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.399     ; 1.505      ;
; 17.033 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.399     ; 1.505      ;
; 17.033 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.399     ; 1.505      ;
; 17.033 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.399     ; 1.505      ;
; 17.033 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.399     ; 1.505      ;
; 17.033 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.399     ; 1.505      ;
; 17.033 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.399     ; 1.505      ;
; 17.215 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[1]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.402     ; 1.320      ;
; 17.215 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[2]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.402     ; 1.320      ;
; 17.576 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.965      ;
; 17.576 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.965      ;
; 17.576 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.965      ;
; 17.576 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.965      ;
; 17.576 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.965      ;
; 17.576 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.965      ;
; 17.576 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.965      ;
; 17.576 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.965      ;
; 17.576 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.965      ;
; 17.576 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.965      ;
; 17.576 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.965      ;
; 17.576 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.965      ;
; 17.576 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.965      ;
; 17.576 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.965      ;
; 17.576 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.965      ;
; 17.580 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_back                                    ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.961      ;
; 17.580 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|high_byte                                    ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.961      ;
; 17.580 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.961      ;
; 17.580 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[0]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.961      ;
; 17.580 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[3]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.961      ;
; 17.580 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_go                                       ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.961      ;
; 17.580 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_back_d                                  ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.961      ;
; 17.580 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|high_byte_d                                  ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 20.000       ; -1.396     ; 0.961      ;
+--------+--------------------------------+----------------------------------------------------------------------------+--------------+------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'CLOCK_50'                                                                                                              ;
+--------+--------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                      ; To Node                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; 18.410 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[19] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 1.537      ;
; 18.410 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[21] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 1.537      ;
; 18.410 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 1.537      ;
; 18.410 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 1.537      ;
; 18.564 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.039     ; 1.384      ;
; 18.832 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.042     ; 1.113      ;
; 18.832 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.042     ; 1.113      ;
; 18.832 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.042     ; 1.113      ;
; 18.832 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.042     ; 1.113      ;
; 18.845 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.041     ; 1.101      ;
; 18.845 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.041     ; 1.101      ;
; 18.845 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.041     ; 1.101      ;
; 18.845 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.041     ; 1.101      ;
; 18.845 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.041     ; 1.101      ;
; 18.845 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.041     ; 1.101      ;
; 18.845 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.041     ; 1.101      ;
; 18.845 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.041     ; 1.101      ;
; 18.845 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.041     ; 1.101      ;
; 18.845 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.041     ; 1.101      ;
; 18.845 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.041     ; 1.101      ;
; 18.845 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.041     ; 1.101      ;
; 18.845 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.041     ; 1.101      ;
; 18.845 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.041     ; 1.101      ;
; 18.845 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.041     ; 1.101      ;
+--------+--------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'CLOCK_50'                                                                                                              ;
+-------+--------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                      ; To Node                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.830 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[2]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 0.945      ;
; 0.830 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[3]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 0.945      ;
; 0.830 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[5]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 0.945      ;
; 0.830 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[8]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 0.945      ;
; 0.830 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[9]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 0.945      ;
; 0.830 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[10] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 0.945      ;
; 0.830 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[11] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 0.945      ;
; 0.830 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[12] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 0.945      ;
; 0.830 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[13] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 0.945      ;
; 0.830 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[14] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 0.945      ;
; 0.830 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[16] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 0.945      ;
; 0.830 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[17] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 0.945      ;
; 0.830 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[18] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 0.945      ;
; 0.830 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[20] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 0.945      ;
; 0.830 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[0]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 0.945      ;
; 0.840 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[1]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.030      ; 0.954      ;
; 0.840 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[4]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.030      ; 0.954      ;
; 0.840 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[6]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.030      ; 0.954      ;
; 0.840 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[7]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.030      ; 0.954      ;
; 1.075 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[15] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.033      ; 1.192      ;
; 1.197 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[19] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.032      ; 1.313      ;
; 1.197 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[21] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.032      ; 1.313      ;
; 1.197 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[22] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.032      ; 1.313      ;
; 1.197 ; reset_delay:u_reset_delay|oRST ; led_driver:u_led_driver|int2_count[23] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.032      ; 1.313      ;
+-------+--------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                               ;
+-------+--------------------------------+----------------------------------------------------------------------------+--------------+------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                      ; To Node                                                                    ; Launch Clock ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------+----------------------------------------------------------------------------+--------------+------------------------------------------------------+--------------+------------+------------+
; 1.739 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_back                                    ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.821      ;
; 1.739 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|high_byte                                    ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.821      ;
; 1.739 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.821      ;
; 1.739 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[0]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.821      ;
; 1.739 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[3]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.821      ;
; 1.739 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_go                                       ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.821      ;
; 1.739 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_back_d                                  ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.821      ;
; 1.739 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|high_byte_d                                  ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.821      ;
; 1.741 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.823      ;
; 1.741 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.823      ;
; 1.741 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.823      ;
; 1.741 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.823      ;
; 1.741 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.823      ;
; 1.741 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.823      ;
; 1.741 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.823      ;
; 1.741 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.823      ;
; 1.741 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.823      ;
; 1.741 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.823      ;
; 1.741 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.823      ;
; 1.741 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.823      ;
; 1.741 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.823      ;
; 1.741 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.823      ;
; 1.741 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.102     ; 0.823      ;
; 2.043 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[1]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.108     ; 1.119      ;
; 2.043 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|clear_status_d[2]                            ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.108     ; 1.119      ;
; 2.193 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.105     ; 1.272      ;
; 2.193 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.105     ; 1.272      ;
; 2.193 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[3] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.105     ; 1.272      ;
; 2.193 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.105     ; 1.272      ;
; 2.193 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.105     ; 1.272      ;
; 2.193 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.105     ; 1.272      ;
; 2.193 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.105     ; 1.272      ;
; 2.193 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.105     ; 1.272      ;
; 2.193 ; reset_delay:u_reset_delay|oRST ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ; CLOCK_50     ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.105     ; 1.272      ;
+-------+--------------------------------+----------------------------------------------------------------------------+--------------+------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                                                                                             ;
+-------+--------------+----------------+-----------------+----------+------------+----------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                         ;
+-------+--------------+----------------+-----------------+----------+------------+----------------------------------------------------------------+
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[0]                          ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[10]                         ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[11]                         ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[12]                         ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[13]                         ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[14]                         ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[15]                         ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[16]                         ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[17]                         ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[18]                         ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[19]                         ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[1]                          ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[20]                         ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[21]                         ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[22]                         ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[23]                         ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[2]                          ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[3]                          ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[4]                          ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[5]                          ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[6]                          ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[7]                          ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[8]                          ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_count[9]                          ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_d[0]                              ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; led_driver:u_led_driver|int2_d[1]                              ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[0]                              ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[10]                             ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[11]                             ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[12]                             ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[13]                             ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[14]                             ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[15]                             ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[16]                             ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[17]                             ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[18]                             ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[19]                             ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[1]                              ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[20]                             ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[2]                              ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[3]                              ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[4]                              ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[5]                              ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[6]                              ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[7]                              ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[8]                              ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|cont[9]                              ;
; 9.273 ; 9.457        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; reset_delay:u_reset_delay|oRST                                 ;
; 9.416 ; 9.416        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0]           ;
; 9.416 ; 9.416        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[1]           ;
; 9.416 ; 9.416        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|observablevcoout ;
; 9.449 ; 9.449        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; CLOCK_50~input|o                                               ;
; 9.452 ; 9.452        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[1]|clk                                 ;
; 9.452 ; 9.452        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[4]|clk                                 ;
; 9.452 ; 9.452        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[6]|clk                                 ;
; 9.452 ; 9.452        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[7]|clk                                 ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[0]|clk                                 ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[10]|clk                                ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[11]|clk                                ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[12]|clk                                ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[13]|clk                                ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[14]|clk                                ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[15]|clk                                ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[16]|clk                                ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[17]|clk                                ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[18]|clk                                ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[19]|clk                                ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[20]|clk                                ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[21]|clk                                ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[22]|clk                                ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[23]|clk                                ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[2]|clk                                 ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[3]|clk                                 ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[5]|clk                                 ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[8]|clk                                 ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_count[9]|clk                                 ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_d[0]|clk                                     ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_led_driver|int2_d[1]|clk                                     ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[0]|clk                                      ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[10]|clk                                     ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[11]|clk                                     ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[12]|clk                                     ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[13]|clk                                     ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[14]|clk                                     ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[15]|clk                                     ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[16]|clk                                     ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[17]|clk                                     ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[18]|clk                                     ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[19]|clk                                     ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[1]|clk                                      ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[20]|clk                                     ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[2]|clk                                      ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[3]|clk                                      ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[4]|clk                                      ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[5]|clk                                      ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[6]|clk                                      ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[7]|clk                                      ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[8]|clk                                      ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|cont[9]|clk                                      ;
; 9.453 ; 9.453        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; u_reset_delay|oRST|clk                                         ;
+-------+--------------+----------------+-----------------+----------+------------+----------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'u_spipll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                            ;
+---------+--------------+----------------+------------------+------------------------------------------------------+------------+----------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock                                                ; Clock Edge ; Target                                                                     ;
+---------+--------------+----------------+------------------+------------------------------------------------------+------------+----------------------------------------------------------------------------+
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status                                 ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status_d[0]                            ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status_d[3]                            ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|high_byte                                    ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|high_byte_d                                  ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|low_byte_data[5]                             ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|low_byte_data[6]                             ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|low_byte_data[7]                             ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_L[5]                                   ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[0]                                  ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[10]                                 ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[11]                                 ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[12]                                 ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[13]                                 ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[15]                                 ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[1]                                  ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[2]                                  ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[3]                                  ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[4]                                  ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[5]                                  ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[6]                                  ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[8]                                  ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[9]                                  ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_back                                    ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_back_d                                  ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_ready                                   ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[0] ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[1] ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[2] ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[3] ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[4] ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[5] ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[6] ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|oS2P_DATA[7] ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[0] ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[1] ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[2] ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count[3] ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_controller:u_spi_controller|spi_count_en ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|spi_go                                       ;
; 249.782 ; 249.998      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status_d[1]                            ;
; 249.782 ; 249.998      ; 0.216          ; High Pulse Width ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status_d[2]                            ;
; 249.815 ; 249.999      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status_d[1]                            ;
; 249.815 ; 249.999      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status_d[2]                            ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status                                 ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status_d[0]                            ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|clear_status_d[3]                            ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|high_byte                                    ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|high_byte_d                                  ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[0]                                 ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[1]                                 ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[2]                                 ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|ini_index[3]                                 ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_H[0]                                   ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_H[1]                                   ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_L[5]                                   ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_L[6]                                   ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|oDATA_L[7]                                   ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[8]                                  ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|p2s_data[9]                                  ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_back                                    ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_back_d                                  ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[0]                           ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[10]                          ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[11]                          ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[12]                          ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[13]                          ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[14]                          ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[1]                           ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[2]                           ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[3]                           ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[4]                           ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[5]                           ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[6]                           ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[7]                           ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[8]                           ;
; 249.816 ; 250.000      ; 0.184          ; Low Pulse Width  ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; spi_ee_config:u_spi_ee_config|read_idle_count[9]                           ;
+---------+--------------+----------------+------------------+------------------------------------------------------+------------+----------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                         ;
+--------------+------------+----------+----------+------------+------------------------------------------------------+
; Data Port    ; Clock Port ; Rise     ; Fall     ; Clock Edge ; Clock Reference                                      ;
+--------------+------------+----------+----------+------------+------------------------------------------------------+
; G_SENSOR_INT ; CLOCK_50   ; 0.252    ; 0.675    ; Rise       ; CLOCK_50                                             ;
; G_SENSOR_INT ; CLOCK_50   ; -197.387 ; -196.981 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SDAT     ; CLOCK_50   ; -197.728 ; -196.967 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
+--------------+------------+----------+----------+------------+------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                        ;
+--------------+------------+---------+---------+------------+------------------------------------------------------+
; Data Port    ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                      ;
+--------------+------------+---------+---------+------------+------------------------------------------------------+
; G_SENSOR_INT ; CLOCK_50   ; -0.077  ; -0.505  ; Rise       ; CLOCK_50                                             ;
; G_SENSOR_INT ; CLOCK_50   ; 198.208 ; 197.856 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SDAT     ; CLOCK_50   ; 198.134 ; 197.387 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
+--------------+------------+---------+---------+------------+------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                              ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+
; Data Port     ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                      ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+
; LED[*]        ; CLOCK_50   ; 7.245   ; 7.294   ; Rise       ; CLOCK_50                                             ;
;  LED[0]       ; CLOCK_50   ; 4.957   ; 4.931   ; Rise       ; CLOCK_50                                             ;
;  LED[1]       ; CLOCK_50   ; 5.215   ; 5.220   ; Rise       ; CLOCK_50                                             ;
;  LED[2]       ; CLOCK_50   ; 4.807   ; 4.884   ; Rise       ; CLOCK_50                                             ;
;  LED[3]       ; CLOCK_50   ; 5.345   ; 5.274   ; Rise       ; CLOCK_50                                             ;
;  LED[4]       ; CLOCK_50   ; 5.538   ; 5.484   ; Rise       ; CLOCK_50                                             ;
;  LED[5]       ; CLOCK_50   ; 5.838   ; 5.990   ; Rise       ; CLOCK_50                                             ;
;  LED[6]       ; CLOCK_50   ; 5.269   ; 5.183   ; Rise       ; CLOCK_50                                             ;
;  LED[7]       ; CLOCK_50   ; 7.245   ; 7.294   ; Rise       ; CLOCK_50                                             ;
; G_SENSOR_CS_N ; CLOCK_50   ; 202.467 ; 202.395 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SCLK      ; CLOCK_50   ; 202.977 ; 202.925 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SDAT      ; CLOCK_50   ; 204.364 ; 204.413 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; LED[*]        ; CLOCK_50   ; 206.527 ; 206.548 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[0]       ; CLOCK_50   ; 203.874 ; 204.003 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[1]       ; CLOCK_50   ; 204.304 ; 204.336 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[2]       ; CLOCK_50   ; 204.102 ; 204.206 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[3]       ; CLOCK_50   ; 204.392 ; 204.457 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[4]       ; CLOCK_50   ; 204.585 ; 204.667 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[5]       ; CLOCK_50   ; 205.430 ; 205.620 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[6]       ; CLOCK_50   ; 204.551 ; 204.437 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[7]       ; CLOCK_50   ; 206.527 ; 206.548 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SCLK      ; CLOCK_50   ; 168.995 ;         ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[1] ;
; I2C_SCLK      ; CLOCK_50   ;         ; 169.028 ; Fall       ; u_spipll|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                      ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+
; Data Port     ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                      ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+
; LED[*]        ; CLOCK_50   ; 4.455   ; 4.419   ; Rise       ; CLOCK_50                                             ;
;  LED[0]       ; CLOCK_50   ; 4.543   ; 4.589   ; Rise       ; CLOCK_50                                             ;
;  LED[1]       ; CLOCK_50   ; 4.545   ; 4.588   ; Rise       ; CLOCK_50                                             ;
;  LED[2]       ; CLOCK_50   ; 4.455   ; 4.419   ; Rise       ; CLOCK_50                                             ;
;  LED[3]       ; CLOCK_50   ; 4.673   ; 4.625   ; Rise       ; CLOCK_50                                             ;
;  LED[4]       ; CLOCK_50   ; 4.860   ; 4.828   ; Rise       ; CLOCK_50                                             ;
;  LED[5]       ; CLOCK_50   ; 5.569   ; 5.620   ; Rise       ; CLOCK_50                                             ;
;  LED[6]       ; CLOCK_50   ; 4.485   ; 4.477   ; Rise       ; CLOCK_50                                             ;
;  LED[7]       ; CLOCK_50   ; 6.613   ; 6.755   ; Rise       ; CLOCK_50                                             ;
; G_SENSOR_CS_N ; CLOCK_50   ; 202.148 ; 202.081 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SCLK      ; CLOCK_50   ; 202.616 ; 202.570 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SDAT      ; CLOCK_50   ; 202.414 ; 202.416 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; LED[*]        ; CLOCK_50   ; 202.541 ; 202.615 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[0]       ; CLOCK_50   ; 202.996 ; 203.096 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[1]       ; CLOCK_50   ; 203.242 ; 203.406 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[2]       ; CLOCK_50   ; 202.541 ; 202.615 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[3]       ; CLOCK_50   ; 202.888 ; 203.000 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[4]       ; CLOCK_50   ; 203.051 ; 203.051 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[5]       ; CLOCK_50   ; 203.974 ; 204.051 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[6]       ; CLOCK_50   ; 202.974 ; 202.814 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[7]       ; CLOCK_50   ; 205.131 ; 205.186 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SCLK      ; CLOCK_50   ; 168.693 ;         ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[1] ;
; I2C_SCLK      ; CLOCK_50   ;         ; 168.722 ; Fall       ; u_spipll|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+


+------------------------------------------------------------+
; Propagation Delay                                          ;
+--------------+-------------+-------+-------+-------+-------+
; Input Port   ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+--------------+-------------+-------+-------+-------+-------+
; G_SENSOR_INT ; LED[0]      ; 4.402 ; 4.839 ; 5.226 ; 4.900 ;
; G_SENSOR_INT ; LED[1]      ; 5.337 ; 5.236 ; 5.597 ; 5.765 ;
; G_SENSOR_INT ; LED[2]      ; 5.049 ; 5.135 ; 5.507 ; 5.611 ;
; G_SENSOR_INT ; LED[3]      ; 5.370 ; 5.271 ; 5.511 ; 5.862 ;
; G_SENSOR_INT ; LED[4]      ; 5.563 ; 5.485 ; 5.707 ; 6.072 ;
; G_SENSOR_INT ; LED[5]      ; 6.377 ; 6.549 ; 6.835 ; 7.025 ;
; G_SENSOR_INT ; LED[6]      ; 4.940 ; 5.415 ; 5.956 ; 5.135 ;
; G_SENSOR_INT ; LED[7]      ; 6.562 ; 7.526 ; 7.932 ; 7.010 ;
+--------------+-------------+-------+-------+-------+-------+


+------------------------------------------------------------+
; Minimum Propagation Delay                                  ;
+--------------+-------------+-------+-------+-------+-------+
; Input Port   ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+--------------+-------------+-------+-------+-------+-------+
; G_SENSOR_INT ; LED[0]      ; 4.253 ; 4.627 ; 4.917 ; 4.751 ;
; G_SENSOR_INT ; LED[1]      ; 4.918 ; 4.694 ; 5.042 ; 5.358 ;
; G_SENSOR_INT ; LED[2]      ; 4.354 ; 4.369 ; 4.717 ; 4.882 ;
; G_SENSOR_INT ; LED[3]      ; 4.354 ; 4.420 ; 4.793 ; 4.852 ;
; G_SENSOR_INT ; LED[4]      ; 4.545 ; 4.628 ; 4.984 ; 5.060 ;
; G_SENSOR_INT ; LED[5]      ; 5.669 ; 5.786 ; 6.032 ; 6.299 ;
; G_SENSOR_INT ; LED[6]      ; 4.569 ; 4.124 ; 4.685 ; 4.802 ;
; G_SENSOR_INT ; LED[7]      ; 6.377 ; 6.717 ; 7.041 ; 6.841 ;
+--------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                            ;
+-----------+------------+---------+---------+------------+------------------------------------------------------+
; Data Port ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                      ;
+-----------+------------+---------+---------+------------+------------------------------------------------------+
; I2C_SDAT  ; CLOCK_50   ; 203.044 ; 202.951 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+---------+---------+------------+------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                    ;
+-----------+------------+---------+---------+------------+------------------------------------------------------+
; Data Port ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                      ;
+-----------+------------+---------+---------+------------+------------------------------------------------------+
; I2C_SDAT  ; CLOCK_50   ; 202.378 ; 202.285 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+---------+---------+------------+------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                               ;
+-----------+------------+-----------+-----------+------------+------------------------------------------------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                      ;
+-----------+------------+-----------+-----------+------------+------------------------------------------------------+
; I2C_SDAT  ; CLOCK_50   ; 202.954   ; 203.047   ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-----------+-----------+------------+------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                       ;
+-----------+------------+-----------+-----------+------------+------------------------------------------------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                      ;
+-----------+------------+-----------+-----------+------------+------------------------------------------------------+
; I2C_SDAT  ; CLOCK_50   ; 202.396   ; 202.489   ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-----------+-----------+------------+------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                               ;
+-------------------------------------------------------+--------+-------+----------+---------+---------------------+
; Clock                                                 ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+-------------------------------------------------------+--------+-------+----------+---------+---------------------+
; Worst-case Slack                                      ; 15.095 ; 0.187 ; 15.083   ; 0.830   ; 9.273               ;
;  CLOCK_50                                             ; 16.160 ; 0.187 ; 17.330   ; 0.830   ; 9.273               ;
;  u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 15.095 ; 0.188 ; 15.083   ; 1.739   ; 249.744             ;
; Design-wide TNS                                       ; 0.0    ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
;  CLOCK_50                                             ; 0.000  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 0.000  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
+-------------------------------------------------------+--------+-------+----------+---------+---------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                         ;
+--------------+------------+----------+----------+------------+------------------------------------------------------+
; Data Port    ; Clock Port ; Rise     ; Fall     ; Clock Edge ; Clock Reference                                      ;
+--------------+------------+----------+----------+------------+------------------------------------------------------+
; G_SENSOR_INT ; CLOCK_50   ; 0.360    ; 0.675    ; Rise       ; CLOCK_50                                             ;
; G_SENSOR_INT ; CLOCK_50   ; -195.523 ; -195.437 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SDAT     ; CLOCK_50   ; -196.094 ; -195.565 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
+--------------+------------+----------+----------+------------+------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                        ;
+--------------+------------+---------+---------+------------+------------------------------------------------------+
; Data Port    ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                      ;
+--------------+------------+---------+---------+------------+------------------------------------------------------+
; G_SENSOR_INT ; CLOCK_50   ; -0.056  ; -0.232  ; Rise       ; CLOCK_50                                             ;
; G_SENSOR_INT ; CLOCK_50   ; 198.208 ; 197.856 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SDAT     ; CLOCK_50   ; 198.134 ; 197.387 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
+--------------+------------+---------+---------+------------+------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                              ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+
; Data Port     ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                      ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+
; LED[*]        ; CLOCK_50   ; 11.650  ; 11.872  ; Rise       ; CLOCK_50                                             ;
;  LED[0]       ; CLOCK_50   ; 8.480   ; 8.381   ; Rise       ; CLOCK_50                                             ;
;  LED[1]       ; CLOCK_50   ; 8.953   ; 8.863   ; Rise       ; CLOCK_50                                             ;
;  LED[2]       ; CLOCK_50   ; 8.143   ; 8.140   ; Rise       ; CLOCK_50                                             ;
;  LED[3]       ; CLOCK_50   ; 9.162   ; 8.984   ; Rise       ; CLOCK_50                                             ;
;  LED[4]       ; CLOCK_50   ; 9.538   ; 9.380   ; Rise       ; CLOCK_50                                             ;
;  LED[5]       ; CLOCK_50   ; 9.302   ; 9.619   ; Rise       ; CLOCK_50                                             ;
;  LED[6]       ; CLOCK_50   ; 8.870   ; 8.850   ; Rise       ; CLOCK_50                                             ;
;  LED[7]       ; CLOCK_50   ; 11.650  ; 11.872  ; Rise       ; CLOCK_50                                             ;
; G_SENSOR_CS_N ; CLOCK_50   ; 204.141 ; 204.127 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SCLK      ; CLOCK_50   ; 205.179 ; 205.000 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SDAT      ; CLOCK_50   ; 207.585 ; 207.548 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; LED[*]        ; CLOCK_50   ; 210.518 ; 210.826 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[0]       ; CLOCK_50   ; 206.798 ; 206.800 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[1]       ; CLOCK_50   ; 207.528 ; 207.415 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[2]       ; CLOCK_50   ; 207.155 ; 207.133 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[3]       ; CLOCK_50   ; 207.732 ; 207.563 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[4]       ; CLOCK_50   ; 208.108 ; 207.959 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[5]       ; CLOCK_50   ; 208.840 ; 209.156 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[6]       ; CLOCK_50   ; 207.738 ; 207.804 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[7]       ; CLOCK_50   ; 210.518 ; 210.826 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SCLK      ; CLOCK_50   ; 170.725 ;         ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[1] ;
; I2C_SCLK      ; CLOCK_50   ;         ; 170.590 ; Fall       ; u_spipll|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                      ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+
; Data Port     ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                      ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+
; LED[*]        ; CLOCK_50   ; 4.455   ; 4.419   ; Rise       ; CLOCK_50                                             ;
;  LED[0]       ; CLOCK_50   ; 4.543   ; 4.589   ; Rise       ; CLOCK_50                                             ;
;  LED[1]       ; CLOCK_50   ; 4.545   ; 4.588   ; Rise       ; CLOCK_50                                             ;
;  LED[2]       ; CLOCK_50   ; 4.455   ; 4.419   ; Rise       ; CLOCK_50                                             ;
;  LED[3]       ; CLOCK_50   ; 4.673   ; 4.625   ; Rise       ; CLOCK_50                                             ;
;  LED[4]       ; CLOCK_50   ; 4.860   ; 4.828   ; Rise       ; CLOCK_50                                             ;
;  LED[5]       ; CLOCK_50   ; 5.569   ; 5.620   ; Rise       ; CLOCK_50                                             ;
;  LED[6]       ; CLOCK_50   ; 4.485   ; 4.477   ; Rise       ; CLOCK_50                                             ;
;  LED[7]       ; CLOCK_50   ; 6.613   ; 6.755   ; Rise       ; CLOCK_50                                             ;
; G_SENSOR_CS_N ; CLOCK_50   ; 202.148 ; 202.081 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SCLK      ; CLOCK_50   ; 202.616 ; 202.570 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SDAT      ; CLOCK_50   ; 202.414 ; 202.416 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; LED[*]        ; CLOCK_50   ; 202.541 ; 202.615 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[0]       ; CLOCK_50   ; 202.996 ; 203.096 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[1]       ; CLOCK_50   ; 203.242 ; 203.406 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[2]       ; CLOCK_50   ; 202.541 ; 202.615 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[3]       ; CLOCK_50   ; 202.888 ; 203.000 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[4]       ; CLOCK_50   ; 203.051 ; 203.051 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[5]       ; CLOCK_50   ; 203.974 ; 204.051 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[6]       ; CLOCK_50   ; 202.974 ; 202.814 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
;  LED[7]       ; CLOCK_50   ; 205.131 ; 205.186 ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ;
; I2C_SCLK      ; CLOCK_50   ; 168.693 ;         ; Rise       ; u_spipll|altpll_component|auto_generated|pll1|clk[1] ;
; I2C_SCLK      ; CLOCK_50   ;         ; 168.722 ; Fall       ; u_spipll|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+---------+---------+------------+------------------------------------------------------+


+----------------------------------------------------------------+
; Progagation Delay                                              ;
+--------------+-------------+--------+--------+--------+--------+
; Input Port   ; Output Port ; RR     ; RF     ; FR     ; FF     ;
+--------------+-------------+--------+--------+--------+--------+
; G_SENSOR_INT ; LED[0]      ; 7.474  ; 8.106  ; 8.331  ; 7.597  ;
; G_SENSOR_INT ; LED[1]      ; 9.115  ; 8.787  ; 9.009  ; 9.196  ;
; G_SENSOR_INT ; LED[2]      ; 8.662  ; 8.640  ; 8.812  ; 8.822  ;
; G_SENSOR_INT ; LED[3]      ; 9.239  ; 8.792  ; 8.942  ; 9.302  ;
; G_SENSOR_INT ; LED[4]      ; 9.615  ; 9.191  ; 9.320  ; 9.698  ;
; G_SENSOR_INT ; LED[5]      ; 10.347 ; 10.663 ; 10.497 ; 10.845 ;
; G_SENSOR_INT ; LED[6]      ; 8.193  ; 9.311  ; 9.477  ; 8.244  ;
; G_SENSOR_INT ; LED[7]      ; 10.389 ; 12.333 ; 12.257 ; 10.791 ;
+--------------+-------------+--------+--------+--------+--------+


+------------------------------------------------------------+
; Minimum Progagation Delay                                  ;
+--------------+-------------+-------+-------+-------+-------+
; Input Port   ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+--------------+-------------+-------+-------+-------+-------+
; G_SENSOR_INT ; LED[0]      ; 4.253 ; 4.627 ; 4.917 ; 4.751 ;
; G_SENSOR_INT ; LED[1]      ; 4.918 ; 4.694 ; 5.042 ; 5.358 ;
; G_SENSOR_INT ; LED[2]      ; 4.354 ; 4.369 ; 4.717 ; 4.882 ;
; G_SENSOR_INT ; LED[3]      ; 4.354 ; 4.420 ; 4.793 ; 4.852 ;
; G_SENSOR_INT ; LED[4]      ; 4.545 ; 4.628 ; 4.984 ; 5.060 ;
; G_SENSOR_INT ; LED[5]      ; 5.669 ; 5.786 ; 6.032 ; 6.299 ;
; G_SENSOR_INT ; LED[6]      ; 4.569 ; 4.124 ; 4.685 ; 4.802 ;
; G_SENSOR_INT ; LED[7]      ; 6.377 ; 6.717 ; 7.041 ; 6.841 ;
+--------------+-------------+-------+-------+-------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; LED[0]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED[1]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED[2]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED[3]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED[4]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED[5]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED[6]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED[7]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; G_SENSOR_CS_N ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; I2C_SCLK      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; I2C_SDAT      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_nCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+----------------------------------------------------------------------------+
; Input Transition Times                                                     ;
+-------------------------+--------------+-----------------+-----------------+
; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; KEY[1]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; I2C_SDAT                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; G_SENSOR_INT            ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CLOCK_50                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; KEY[0]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_DATA0~          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+-------------------------+--------------+-----------------+-----------------+


 
; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
 
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
 
; LED[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; LED[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; LED[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; LED[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; LED[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; LED[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.09 V              ; -0.0119 V           ; 0.277 V                              ; 0.297 V                              ; 4.54e-09 s                  ; 3.32e-09 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.09 V             ; -0.0119 V          ; 0.277 V                             ; 0.297 V                             ; 4.54e-09 s                 ; 3.32e-09 s                 ; No                        ; No                        ;
; LED[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.16 V              ; -0.11 V             ; 0.302 V                              ; 0.22 V                               ; 4.82e-10 s                  ; 4.27e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.16 V             ; -0.11 V            ; 0.302 V                             ; 0.22 V                              ; 4.82e-10 s                 ; 4.27e-10 s                 ; Yes                       ; No                        ;
; LED[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.09 V              ; -0.0119 V           ; 0.277 V                              ; 0.297 V                              ; 4.54e-09 s                  ; 3.32e-09 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.09 V             ; -0.0119 V          ; 0.277 V                             ; 0.297 V                             ; 4.54e-09 s                 ; 3.32e-09 s                 ; No                        ; No                        ;
; G_SENSOR_CS_N ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.16 V              ; -0.11 V             ; 0.302 V                              ; 0.22 V                               ; 4.82e-10 s                  ; 4.27e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.16 V             ; -0.11 V            ; 0.302 V                             ; 0.22 V                              ; 4.82e-10 s                 ; 4.27e-10 s                 ; Yes                       ; No                        ;
; I2C_SCLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; I2C_SDAT      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.05e-09 V                   ; 3.21 V              ; -0.181 V            ; 0.16 V                               ; 0.253 V                              ; 2.77e-10 s                  ; 2.32e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 8.05e-09 V                  ; 3.21 V             ; -0.181 V           ; 0.16 V                              ; 0.253 V                             ; 2.77e-10 s                 ; 2.32e-10 s                 ; No                        ; Yes                       ;
; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.61e-09 V                   ; 2.38 V              ; -0.00274 V          ; 0.141 V                              ; 0.006 V                              ; 4.7e-10 s                   ; 6.02e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.61e-09 V                  ; 2.38 V             ; -0.00274 V         ; 0.141 V                             ; 0.006 V                             ; 4.7e-10 s                  ; 6.02e-10 s                 ; Yes                       ; Yes                       ;
 


 
; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
 
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
 
; LED[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; LED[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; LED[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; LED[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; LED[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; LED[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.08 V              ; -0.00666 V          ; 0.298 V                              ; 0.277 V                              ; 5.29e-09 s                  ; 4.2e-09 s                   ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.08 V             ; -0.00666 V         ; 0.298 V                             ; 0.277 V                             ; 5.29e-09 s                 ; 4.2e-09 s                  ; Yes                       ; No                        ;
; LED[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.13 V              ; -0.0781 V           ; 0.202 V                              ; 0.359 V                              ; 6.54e-10 s                  ; 5e-10 s                     ; No                         ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.13 V             ; -0.0781 V          ; 0.202 V                             ; 0.359 V                             ; 6.54e-10 s                 ; 5e-10 s                    ; No                        ; No                        ;
; LED[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.08 V              ; -0.00666 V          ; 0.298 V                              ; 0.277 V                              ; 5.29e-09 s                  ; 4.2e-09 s                   ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.08 V             ; -0.00666 V         ; 0.298 V                             ; 0.277 V                             ; 5.29e-09 s                 ; 4.2e-09 s                  ; Yes                       ; No                        ;
; G_SENSOR_CS_N ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.13 V              ; -0.0781 V           ; 0.202 V                              ; 0.359 V                              ; 6.54e-10 s                  ; 5e-10 s                     ; No                         ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.13 V             ; -0.0781 V          ; 0.202 V                             ; 0.359 V                             ; 6.54e-10 s                 ; 5e-10 s                    ; No                        ; No                        ;
; I2C_SCLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; I2C_SDAT      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.02e-06 V                   ; 3.14 V              ; -0.123 V            ; 0.134 V                              ; 0.323 V                              ; 3.02e-10 s                  ; 2.85e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 1.02e-06 V                  ; 3.14 V             ; -0.123 V           ; 0.134 V                             ; 0.323 V                             ; 3.02e-10 s                 ; 2.85e-10 s                 ; Yes                       ; No                        ;
; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.45e-07 V                   ; 2.35 V              ; -0.00643 V          ; 0.081 V                              ; 0.031 V                              ; 5.31e-10 s                  ; 7.59e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.45e-07 V                  ; 2.35 V             ; -0.00643 V         ; 0.081 V                             ; 0.031 V                             ; 5.31e-10 s                 ; 7.59e-10 s                 ; Yes                       ; Yes                       ;
 


 
; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
 
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
 
; LED[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; LED[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; LED[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; LED[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; LED[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; LED[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.48 V              ; -0.0162 V           ; 0.354 V                              ; 0.317 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.48 V             ; -0.0162 V          ; 0.354 V                             ; 0.317 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; LED[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.6 V               ; -0.127 V            ; 0.302 V                              ; 0.21 V                               ; 4.55e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.6 V              ; -0.127 V           ; 0.302 V                             ; 0.21 V                              ; 4.55e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; LED[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.48 V              ; -0.0162 V           ; 0.354 V                              ; 0.317 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.48 V             ; -0.0162 V          ; 0.354 V                             ; 0.317 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; G_SENSOR_CS_N ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.6 V               ; -0.127 V            ; 0.302 V                              ; 0.21 V                               ; 4.55e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.6 V              ; -0.127 V           ; 0.302 V                             ; 0.21 V                              ; 4.55e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; I2C_SCLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; I2C_SDAT      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.54e-08 V                   ; 3.66 V              ; -0.26 V             ; 0.41 V                               ; 0.32 V                               ; 1.57e-10 s                  ; 2.15e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 6.54e-08 V                  ; 3.66 V             ; -0.26 V            ; 0.41 V                              ; 0.32 V                              ; 1.57e-10 s                 ; 2.15e-10 s                 ; No                        ; Yes                       ;
; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.54e-08 V                   ; 2.7 V               ; -0.00943 V          ; 0.276 V                              ; 0.035 V                              ; 3.19e-10 s                  ; 4.99e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.54e-08 V                  ; 2.7 V              ; -0.00943 V         ; 0.276 V                             ; 0.035 V                             ; 3.19e-10 s                 ; 4.99e-10 s                 ; No                        ; Yes                       ;
 


+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                         ;
+------------------------------------------------------+------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                           ; To Clock                                             ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------------------------------------+------------------------------------------------------+----------+----------+----------+----------+
; CLOCK_50                                             ; CLOCK_50                                             ; 674      ; 0        ; 0        ; 0        ;
; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 31       ; 0        ; 0        ; 0        ;
; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 681      ; 0        ; 0        ; 0        ;
+------------------------------------------------------+------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                          ;
+------------------------------------------------------+------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                           ; To Clock                                             ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------------------------------------+------------------------------------------------------+----------+----------+----------+----------+
; CLOCK_50                                             ; CLOCK_50                                             ; 674      ; 0        ; 0        ; 0        ;
; CLOCK_50                                             ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 31       ; 0        ; 0        ; 0        ;
; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 681      ; 0        ; 0        ; 0        ;
+------------------------------------------------------+------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                            ;
+------------+------------------------------------------------------+----------+----------+----------+----------+
; From Clock ; To Clock                                             ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+------------------------------------------------------+----------+----------+----------+----------+
; CLOCK_50   ; CLOCK_50                                             ; 24       ; 0        ; 0        ; 0        ;
; CLOCK_50   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 34       ; 0        ; 0        ; 0        ;
+------------+------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                             ;
+------------+------------------------------------------------------+----------+----------+----------+----------+
; From Clock ; To Clock                                             ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+------------------------------------------------------+----------+----------+----------+----------+
; CLOCK_50   ; CLOCK_50                                             ; 24       ; 0        ; 0        ; 0        ;
; CLOCK_50   ; u_spipll|altpll_component|auto_generated|pll1|clk[0] ; 34       ; 0        ; 0        ; 0        ;
+------------+------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 3     ; 3    ;
; Unconstrained Input Port Paths  ; 41    ; 41   ;
; Unconstrained Output Ports      ; 11    ; 11   ;
; Unconstrained Output Port Paths ; 84    ; 84   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
    Info: Version 13.0.0 Build 156 04/24/2013 SJ Web Edition
    Info: Processing started: Thu Aug 31 22:57:59 2017
Info: Command: quartus_sta DE0_NANO_G_Sensor -c DE0_NANO_G_Sensor
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'DE_NANO_G_Sensor.SDC'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained generated clocks found in the design. Calling "derive_pll_clocks -create_base_clocks"
Info (332110): Deriving PLL clocks
    Info (332110): create_clock -period 20.000 -waveform {0.000 10.000} -name CLOCK_50 CLOCK_50
    Info (332110): create_generated_clock -source {u_spipll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 25 -phase 144.00 -duty_cycle 50.00 -name {u_spipll|altpll_component|auto_generated|pll1|clk[0]} {u_spipll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {u_spipll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 25 -phase 120.00 -duty_cycle 50.00 -name {u_spipll|altpll_component|auto_generated|pll1|clk[1]} {u_spipll|altpll_component|auto_generated|pll1|clk[1]}
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Info (332146): Worst-case setup slack is 15.095
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    15.095         0.000 u_spipll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    16.160         0.000 CLOCK_50 
Info (332146): Worst-case hold slack is 0.358
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.358         0.000 CLOCK_50 
    Info (332119):     0.358         0.000 u_spipll|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case recovery slack is 15.083
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    15.083         0.000 u_spipll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.330         0.000 CLOCK_50 
Info (332146): Worst-case removal slack is 1.509
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.509         0.000 CLOCK_50 
    Info (332119):     3.110         0.000 u_spipll|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 9.595
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     9.595         0.000 CLOCK_50 
    Info (332119):   249.748         0.000 u_spipll|altpll_component|auto_generated|pll1|clk[0] 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 15.596
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    15.596         0.000 u_spipll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    16.604         0.000 CLOCK_50 
Info (332146): Worst-case hold slack is 0.312
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.312         0.000 CLOCK_50 
    Info (332119):     0.312         0.000 u_spipll|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case recovery slack is 15.632
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    15.632         0.000 u_spipll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.585         0.000 CLOCK_50 
Info (332146): Worst-case removal slack is 1.386
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.386         0.000 CLOCK_50 
    Info (332119):     2.758         0.000 u_spipll|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 9.596
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     9.596         0.000 CLOCK_50 
    Info (332119):   249.744         0.000 u_spipll|altpll_component|auto_generated|pll1|clk[0] 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 17.117
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    17.117         0.000 u_spipll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.793         0.000 CLOCK_50 
Info (332146): Worst-case hold slack is 0.187
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.187         0.000 CLOCK_50 
    Info (332119):     0.188         0.000 u_spipll|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case recovery slack is 17.033
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    17.033         0.000 u_spipll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    18.410         0.000 CLOCK_50 
Info (332146): Worst-case removal slack is 0.830
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.830         0.000 CLOCK_50 
    Info (332119):     1.739         0.000 u_spipll|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 9.273
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     9.273         0.000 CLOCK_50 
    Info (332119):   249.781         0.000 u_spipll|altpll_component|auto_generated|pll1|clk[0] 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 495 megabytes
    Info: Processing ended: Thu Aug 31 22:58:01 2017
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02


